July 15, 2011
4:30 a.m.
On 7/13/11, Gang Lei (雷刚) <gang.lei@mediatek.com> wrote:
Hi :
The SCU can solve all the cache coherency problems?
...
From [1]:
The SCU functions are to: * maintain data cache coherency between the Cortex-A9 processors * initiate L2 AXI memory accesses * arbitrate between Cortex-A9 processors requesting L2 accesses * manage ACP accesses. Note * The Cortex-A9 SCU does not support hardware management of coherency of the instruction cache. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CDDEHDD...