Hi All, I am using Multi-core ARM machine. If I use flush_cache_all() API, will it flush only current CPU cache ?, or flush all cache's of all core's. Thanks
hi: 2011/7/11 naveen yadav <yad.naveen@gmail.com>
Hi All,
I am using Multi-core ARM machine. If I use flush_cache_all() API, will it flush only current CPU cache ?, or flush all cache's of all core's.
Thanks
how about asking this question to linux arm mailing list? -- Regards,
On 7/11/11, naveen yadav <yad.naveen@gmail.com> wrote:
Hi All,
I am using Multi-core ARM machine. If I use flush_cache_all() API, will it flush only current CPU cache ?, or flush all cache's of all core's.
Thanks
_______________________________________________ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Hi! I think, it doesn't matter as soon as SCU is involved.
Hi : The SCU can solve all the cache coherency problems? From: kernelnewbies-bounces@kernelnewbies.org [mailto:kernelnewbies-bounces@kernelnewbies.org] On Behalf Of Vladimir Murzin Sent: 2011年7月11日 17:51 To: naveen yadav Cc: kernelnewbies@kernelnewbies.org Subject: Re: flush_cache_all API On 7/11/11, naveen yadav <yad.naveen@gmail.com> wrote:
Hi All,
I am using Multi-core ARM machine. If I use flush_cache_all() API, will it flush only current CPU cache ?, or flush all cache's of all core's.
Thanks
_______________________________________________ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Hi! I think, it doesn't matter as soon as SCU is involved. _______________________________________________ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
On 7/13/11, Gang Lei (雷刚) <gang.lei@mediatek.com> wrote:
Hi :
The SCU can solve all the cache coherency problems?
...
From [1]:
The SCU functions are to: * maintain data cache coherency between the Cortex-A9 processors * initiate L2 AXI memory accesses * arbitrate between Cortex-A9 processors requesting L2 accesses * manage ACP accesses. Note * The Cortex-A9 SCU does not support hardware management of coherency of the instruction cache. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CDDEHDD...
participants (4)
-
Gang Lei (雷刚) -
loody -
naveen yadav -
Vladimir Murzin