Makefile for a single source file

Hi, I have a single source file which I wrote, implementing a kernel module: helloworld.c In order to built it, I prepared the following Makefile: obj-m += helloworld.o all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean Is it ok ? or should the obj-m parameter be *different* than the the source file (without the *.o suffix) (something like obj-m += hello.o ?) Regards, Kevin