Makefile for a single source file
Hi, I have a single source file which I wrote, implementing a kernel module: helloworld.c In order to built it, I prepared the following Makefile: obj-m += helloworld.o all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean Is it ok ? or should the obj-m parameter be *different* than the the source file (without the *.o suffix) (something like obj-m += hello.o ?) Regards, Kevin
Is this part of the Eudyptula Challenge? On 13 Sep 2014 16:35, "Kevin Wilson" <wkevils@gmail.com> wrote:
Hi, I have a single source file which I wrote, implementing a kernel module: helloworld.c
In order to built it, I prepared the following Makefile:
obj-m += helloworld.o
all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Is it ok ? or should the obj-m parameter be *different* than the the source file (without the *.o suffix) (something like obj-m += hello.o ?)
Regards, Kevin
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Hi, No. This is a newbie question, and I believe this is the right mailing list to get help. Regards, Kevin On Sat, Sep 13, 2014 at 5:36 PM, Kristofer Hallin <kristofer.hallin@gmail.com> wrote:
Is this part of the Eudyptula Challenge?
On 13 Sep 2014 16:35, "Kevin Wilson" <wkevils@gmail.com> wrote:
Hi, I have a single source file which I wrote, implementing a kernel module: helloworld.c
In order to built it, I prepared the following Makefile:
obj-m += helloworld.o
all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Is it ok ? or should the obj-m parameter be *different* than the the source file (without the *.o suffix) (something like obj-m += hello.o ?)
Regards, Kevin
_______________________________________________ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
On Sat, Sep 13, 2014 at 05:34:11PM +0300, Kevin Wilson wrote:
Hi, I have a single source file which I wrote, implementing a kernel module: helloworld.c
In order to built it, I prepared the following Makefile:
obj-m += helloworld.o
all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Is it ok ? or should the obj-m parameter be *different* than the the source file (without the *.o suffix) (something like obj-m += hello.o ?)
Does the above work for you? Have you read the kernel documentation about how to write stand-alone Makefiles? It should answer this question for you, right? thanks, greg k-h
Kevin Wilson <wkevils <at> gmail.com> writes:
Is it ok ? or should the obj-m parameter be *different* than the the source file (without the *.o suffix) (something like obj-m += hello.o ?)
Regards, Kevin
Have you tested it? Test exactly what you are asking and see what happens. That's the best way to learn. Regards BGS
participants (4)
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Bruno Guedes Souto -
Greg KH -
Kevin Wilson -
Kristofer Hallin