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LinuxCon Japan Videos
by Paul Fisher July 16, 2011

July 16, 2011

Can anybody point me at this year's LinuxCon Japan video recordings? Are they available somewhere? I'm aware of the Linus interview, I am intrested in talks and panels. --paul

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Difference between Processors
by Niamathullah sharief July 16, 2011

July 16, 2011

Dear friends, Can anyone tell me what is the exact difference between CISC and RISC processors? Which one is best and how it varies? Please tell me. Thank you

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linux dma apis
by Abhishek Batta July 16, 2011

July 16, 2011

Hello everyone, Please point me to some useful links to start understanding linux dma . Thanks

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change kthread priority
by loody July 15, 2011

July 15, 2011

Dear all: I have some questions about kthread: 1. can we change kthread priority through user mode program? 2. I found some functions that may be helpful. sched_getscheduler sched_setscheduler When I use them in user mode, the return value of sched_setscheduler is fail. there is a thread talking about this, http://www.spinics.net/lists/linux-rt-users/msg06588.html What makes me confuse is "these 2 functions is used in user mode or kernel mode?" -- Regards, -- Regards, -- Regards,

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Questions regarding console drivers..
by sandeep kumar July 15, 2011

July 15, 2011

Hi all, I have gone through the kernel/kernel/printk.c file. And i have the following questions.. I have some rough idea of several things, but i need to conform them 1) What is a console driver? --> My idea is it allows the kernel to input or output the characters to or from a particular device. 2) Why so many command-line consoles are needed? --> (if first qn is right...why cant u use single console to several devices) 3) What is a boot console & real console? 4) How to know how many number of consoles are running at a time? 5) In the boot command line we will pass one console name "console=ttyXXX", other than that where the remaining consoles are being registered? Please answer these questions so that i can have furthur understanding Thank you all.. -- With regards, Sandeep Kumar Anantapalli,

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flush_cache_all API
by naveen yadav July 15, 2011

July 15, 2011

Hi All, I am using Multi-core ARM machine. If I use flush_cache_all() API, will it flush only current CPU cache ?, or flush all cache's of all core's. Thanks

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Puzzled about MDIO issue
by bill July 15, 2011

July 15, 2011

Hi, All I've been reading MDIO code, tiny though but it still puzzled me for its usage. MDIO is an hardware interface for the MAC to set/get PHY configuration/status. Linux manipulates MDIO through: struct net_device ->do_ioctl -> mdio_mii_ioctl -> mdio_read/mdio_write Question: A: Turn an NIC from cold state to running state, is this ioctl must be used to configure the PHY? If so , how? B: what's the usage of this net device ioctl? I found an user-space package mii-tool create a socket first and then use the socket handle for ioctl to query lots of PHY information. Is there any other typical usage of it? thanks bill

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SATA/SAS link speed negotiation
by Peter Hamilton July 14, 2011

July 14, 2011

I'm trying to find out what the negotiated speed is on a SATA port. dmesg reports the negotiated speed, but I'm hoping to find it somewhere in /sys or /proc (or some other tool). Scraping dmesg is a messy process as I'm starting with a block device. I would have to trace the block device to the scsi address and translate that to an ata address. Here's the scsi and block device info from dmesg: scsi 7:0:0:0: Direct-Access ATA WDC WD1600AAJS-2 01.0 PQ: 0 ANSI: 5 sd 7:0:0:0: [sdd] 312581808 512-byte logical blocks: (160 GB/149 GiB) sd 7:0:0:0: [sdd] Write Protect is off sd 7:0:0:0: [sdd] Mode Sense: 00 3a 00 00 sd 7:0:0:0: [sdd] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sd 7:0:0:0: [sdd] Attached SCSI disk sd 7:0:0:0: Attached scsi generic sg3 type 0 Here's the corresponding ata info from dmesg: ata7: SATA link up 3.0 Gbps (SStatus 123 SControl 370) ata7.00: ATA-8: WDC WD1600AAJS-22L7A0, 01.03E01, max UDMA/133 ata7.00: 312581808 sectors, multi 0: LBA48 NCQ (depth 31/32), AA ata7.00: configured for UDMA/133 Finding the SATA link speed in dmesg would be much cleaner than scraping dmesg. Does anyone know where I might find that? Also, for a SAS HBA, the link speed is not reported to dmesg. Does anyone know how to find the link speed for a SAS drive? Thanks, Peter

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driver ring buffer overrun and printf usage
by Amit Nagal July 14, 2011

July 14, 2011

Hi , In my embedded linux-arm target , in a userspace thread , i am reading hid events over usb-hiddev interface (/dev/hiddev) . basically what i do is this : read_thread(){ while(1){ ret = read( "/dev/hiddev" , user_buffer , bytes_to_read); printf("bytes received =%d" , ret ) ; // (printf prints debug message to serial console ); } } now whenever i use the printf statement in read thread , kernel space ring buffer in usb-hid driver is overrun frequently , which results in loss of data send by usb device . if i remove printf in read thread , no overruns are reported in usb-hid driver . that means if printf is used , application read_thread is not able to read data in time which leads to driver ring buffer overrun . does this behaviour of printf points to some problem in embedded linux's scheduler ( printf prints data to debug serial port , and consecutive read() calls in read_thread() are scheduled lately due to that ) ? do the actual implementation of printf involves any kind of sleeps ? kindly share necessary insight wrt above printf usage and driver ring buffer overrun . regards Amit Nagal

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Why is the clear_bit() a specical bitop?
by Parmenides July 14, 2011

July 14, 2011

Hi, When reading asm/bitops.h, I have some questions about bit clear operations. p.s. the link: http://lxr.linux.no/linux+v2.6.34/arch/x86/include/asm/bitops.h The clear_bit() is defined as follows: /** * clear_bit - Clears a bit in memory * @nr: Bit to clear * @addr: Address to start counting from * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() * in order to ensure changes are visible on other processors. */ static __always_inline void clear_bit(int nr, volatile unsigned long *addr) { if (IS_IMMEDIATE(nr)) { asm volatile(LOCK_PREFIX "andb %1,%0" : CONST_MASK_ADDR(nr, addr) : "iq" ((u8)~CONST_MASK(nr))); } else { asm volatile(LOCK_PREFIX "btr %1,%0" : BITOP_ADDR(addr) : "Ir" (nr)); } } 1. Two its parallel funcitons, namely set_bit() and change_bit() contain their memory barriers, while the clear_bit() does not has one. What does make it deserver such a special consideration? 2. How is it used for locking purpose? Is there any example? The clear_bit_unlock() is defined as follows: /* * clear_bit_unlock - Clears a bit in memory * @nr: Bit to clear * @addr: Address to start counting from * * clear_bit() is atomic and implies release semantics before the memory * operation. It can be used for an unlock. */ static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr) { barrier(); clear_bit(nr, addr); } 3. "clear_bit() is atomic and implies ***release semantics*** before the memory operation" What's the meaning of "release semantics"? 4. Why does the barrier() precede the clear_bit()? AFAIK, barrier() will cause memory values reload into registers. Now that the clear_bit() modifies the memory, why is there no a barrier() after the clear_bit()?

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