December 2011 - kernelnewbies@kernelnewbies.org

some questions about log level
by loody June 29, 2012

June 29, 2012

hi all: my questions are below: 1. Can I temporarily let kernel message show in stdout? I google some key word as "console_loglevel" and I found following methods: a. echo 8 > /proc/sys/kernel/printk b. write a simple program which calling "klogctl(8, NULL, level)" Then I purposely connect/disconnect USB, but my console keep quiet. But dmesg shows connect/disconnect messages. 2. what is differences between above a and b methods? Are they not to used to change console_loglevel? 3. is it possible the max level of "console_loglevel" doesn't mean it will show on stdout? -- Thanks for your help

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Changes in block layer for IOScheduler Insertion selection
by mani Feb. 6, 2012

Feb. 6, 2012

Dear All, I am working on linux kernel 2.6.32.9 tegra NVIDIA board. I am getting ~8MBps speed of the Nand disk if i use hdparm hdparm -t /dev/mtdblock3 i made changes in block layer of kernel as below:- block/blk-core.c static inline void add_request(struct request_queue *q, struct request *req) { drive_stat_acct(req, 1); /* * elevator indicated where it wants this request to be * inserted at elevator_merge time */ __elv_add_request(q, req, ELEVATOR_INSERT_BACK, 0); //__elv_add_request(q, req, ELEVATOR_INSERT_SORT, 0); } changed ELEVATOR_INSERT_SORT to ELEVATOR_INSERT_BACK it improves my NAND speed to 10MBps. I am using "noop" I/O scheduler. Will this change have any adverse effect in kernel ? or any other side effect as far as i am using only Nand no Hard disk. Thanks Mani

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serial: 8250: RX hang issue
by Pradeep Kumar Jan. 25, 2012

Jan. 25, 2012

Hi All, I am working on a mobile development platform and performing some stress warm boot tests using UART debug console(which is using serial 8250 driver for console). I am getting device debug console UART RX hang after iterations > 1500. after this issue am not* able to issue any command. Able to see logs though. Later I kept some debug prints in isr and able to see that device is able to generate interrupts when some data is received. So I came to conclusion that some malfunctioning is happening in upper layer not sure which layer has this problem. Can some one give some ideas at which layer I can check? One more observation is when I perform a open and close calls on debug UART port(in my case ttyS0) while device is in UART RX hang state, then I notice the UART console RX again below active and able issue commands from UART console itself.

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Re: GPIO driver module for Jetway NF98 board
by Joan Pau Beltran Jan. 23, 2012

Jan. 23, 2012

Thank you very much for your response. It brings up a lot of useful information. Al 22/12/11 01:15, En/na Josh Cartwright ha escrit: > On Wed, Dec 21, 2011 at 06:34:58PM +0100, Joan Pau Beltran wrote: >> Hi everyone, >> >> I did not find any existing driver for the GPIO port of the Jetway >> NF98 mini-itx board, so I would like to write a module for that, >> using the gpiolib interface. >> >> Since the board documentation does not include any information about >> the GPIOs, I contacted the Jetway support team. However, the only >> answer was the attached code for Windows (NF98GPIO.c). >> As you can see, it seems clear how to set the pin states for output, >> but not how to read them in input mode. I asked again and the >> response was (literally): >>> input sample code: >>> { >>> data= ISA_RW(GPIO_BASE[pin]+0x2,highlow<<pin,1,~(1<<pin)); >>> } >>> //final exit SIO >>> outp(INDEX_PORT,0xaa); >>> return data; >> It makes no sense, and it is very upsetting. >> I would try to read from the same address used for output, but this >> is just an idea to be tested. > I think you're on the right track. In researching this board a little > more, I was able to uncover some information. For the sake of > learning, I've included my steps to discovery here: > > From Jetway's website (http://www.jetwaycomputer.com/NF98.html) I found > that the chipset used in the board is an Intel QM57. > > Searching for datasheets for the Intel QM57 brought me to Intel's site > (http://www.intel.com/content/www/us/en/chipsets/5-chipset-3400-chipset-data…) > Searching the document for GPIO, I found section 5.15.4, "GPIO Registers > Lockdown". The content of the text portion of the section didn't seem > all that relevant, but there is a description of a register set that > seems to match up with the values in your attached example: > Relevant information also appears in sections: 13.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0) 13.1.15 GC—GPIO Control Register (LPC I/F—D31:F0) 13.10 General Purpose I/O Registers Where the functionality of each register is described in detail. > Searching for the symbolic names brings up this document, which looks > like it may describe in more detail how to use this GPIO interface: > > http://download.intel.com/embedded/chipsets/appnote/322174.pdf > After looking at both documents, can you please confirm these ideas: 1.- The GPIO functionality of the jwnf98 comes from a hardware device in the chipset called LPC (Low Pin Cout) controller managed through the LPC Interface Bridge registers (section 9.1 page 366). This LPC controller provides other functionalities, too. 2.- The LPC resides in a PCI bus. 3.- GPIO is managed accessing the registers of the LPC. We should read from and write to these registers according to the notes in 13.10 (GPIO_USE_SEL, GPIO_IO_SEL and GPIO_LVL). Not all the GPIOs are available, only the ones given in the Jetway code. 4.- The GPIO registers of the LPC are mapped to some I/O port, starting at the address specified in the GPIOBASE register. From the first paragraph in section 13.10, page 546: > The control for the general purpose I/O signals is handled through a > 128-byte I/O > space. The base offset for this space is selected by the GPIOBASE > register. 5.- From Jetway code, it seems that the base address in the GPIOBASE register described in 13.1.14 is set by the manufacturer to 0x500. Conversely, the Intel code gets that base address reading the GPIOBASE register. Note that specific pci functions are used for that. If Tech Support info is ok, I do not need to do that, and can simply request the needed i/o ports taking as base offset 0x500. If the above points are ok, I have some doubts related with my previous questions: >> 1. How should I request/release the ports mentioned in the attached >> file? Should I use the request_region/release_region functions from >> linux/ioport.h? In such case, what should I do with the returned >> struct resource? I think I should userequest_region/release_region from linux/ioport.h, and simply ignore the returned resource, is it ok? >> 3. Should/could I use the test_bit, set_bit, clear_bit functions to >> get, set the bit in the needed read/write functions I am writing? Or >> should I use the sequence 'inb - mask the value properly - outb' ? > Nope, as far as I know these bitops only work with memory operands. Is this because we use port-based i/o instead of memory-mapped i/o? Here it goes the code again. The main question is, should the gpio_chip be statically allocated, or it should be created in the init function and destroyed in the exit function? If the latter, how to do that? Thank you very much! #include <linux/module.h> #include <linux/types.h> #include <asm-generic/io.h> #define GPIO_BASE 0x500; /* pin 0 (GPIO 21) is controlled by an specific bit of a different set of ports: */ #define PIN0_FUNCTION GPIO_BASE + 0x2; #define PIN0_DIRECTION GPIO_BASE + 0x6; #define PIN0_STATUS GPIO_BASE + 0xE; #define PIN0_BIT 5; /* pins 1 to 7 (GPIO 33 to 39) correspond to the respective bit on these ports */ #define PINX_FUNCTION GPIO_BASE + 0x30; #define PINX_DIRECTION GPIO_BASE + 0x34; #define PINX_STATUS GPIO_BASE + 0x38; static int jwnf98_gpio_direction_input(struct gpio_chip *gc, unsigned off) { unsigned long dir_add; unsigned bit_off; u8 byte; if (off) { dir_add = PINX_DIRECTION; bit_off = off; } else { dir_add = PIN0_DIRECTION; bit_off = PIN0_BIT; } byte = inb(dir_add); byte |= (1 << bit_off); outb(byte, dir_add); } static int jwnf98_gpio_direction_output(struct gpio_chip *gc, unsigned off, int val) { unsigned long dir_add; unsigned long val_add; unsigned bit_off; u8 byte; if (off) { dir_add = PINX_DIRECTION; val_add = PINX_STATUS; bit_off = off; } else { dir_add = PIN0_DIRECTION; val_add = PIN0_STATUS; bit_off = PIN0_BIT; } byte = inb(dir_add); byte &= ~(1 << bit_off); outb(byte, dir_add); if (val) { byte = inb(val_add); byte |= (1 << bit_off); outb(byte, val_add); } else { byte = inb(val_add); byte &= ~(1 << bit_off); outb(byte, val_add); } } static int jwnf98_gpio_get(struct gpio_chip *gc, unsigned off) { unsigned long add; unsigned bit; u8 byte; if (off) { add = PINX_STATUS; bit = off; } else { add = PIN0_STATUS; bit = PIN0_BIT; } byte = inb(add); byte &= (1 << bit); return !!byte; /* Is the double negation !! needed? */ } static void jwnf98_gpio_set(struct gpio_chip *gc, unsigned off, int val) { unsigned long add; unsigned bit; u8 byte; if (off) { add = PINX_STATUS; bit = off; } else { add = PIN0_STATUS; bit = PIN0_BIT; } byte = inb(add); if (val) byte |= (1 << bit); else byte &= ~(1 << bit); outb(byte, add); } static struct gpio_chip gpio_pins = { .label = "jwnf98", .owner = THIS_MODULE, .direction_input = jwnf98_gpio_direction_input, .get = jwnf98_gpio_get, .direction_output = jwnf98_gpio_direction_output, .set = jwnf98_gpio_set, .dbg_show = jwnf98_gpio_dbg_show, .can_sleep = 0, }; static int __init jwnf98_gpio_init(void) { /* Do preliminar work here: - Request ports? - Create the chip here instead of let it be static? How? - Enable gpio function for each pin? - Something else? */ } static void __exit jwnf98_gpio_exit(void) { /* Do cleanup work here: - Release ports? - Delete the chip if it was created on init function instead of being static? How? - Disable gpio function for each pin? - Something else? */ } module_init(jwnf98_gpio_init); module_exit(jwnf98_gpio_exit); MODULE_DESCRIPTION("Jetway NF98 GPIO driver"); MODULE_LICENSE("GPL"); -- Joan Pau Beltran Grup de Sistemes, Robòtica i Visió - DMI Universitat de les Illes Balears Ctra. Valldemossa, km 7.5 07122 Palma Campus Universitari, edifici Anselm Turmeda Telf (+34) 971 17 28 13 Fax (+34) 971 17 30 03

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Filtering USB storage data in kernel module
by Abhijit Pawar Jan. 12, 2012

Jan. 12, 2012

Hi All, I need to filter the data written/read to and from the USB storage disk. Now the way USB is made known to OS is through SCSI and then respective filesystem ( mostly usbfs). So is there any way I can intercept this stack and have my kernel module invoked so that I will get the data. I have been thinking on two approaches: 1. Use VFS and write a proxy filesystem for USB device which will filter the data. 2. checking SCSI and any intercepting point. I am currently looking at USBMONITOR source code as well. Please let me know if there is any other way to achieve this. Regards, Abhijit Pawar

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help regarding ext4 extend and multiblock allocation
by Swapnil Gaikwad Jan. 4, 2012

Jan. 4, 2012

How the extend is different from block allocation? How it is implemented in ext4? How helpful the multiblock allocation in ext4? Is there is some special cases than ext3 that handled in ext4 for above. -- Regards, Swapnil Gaikwad.

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(no subject)
by Philip Anil-QBW348 Dec. 31, 2011

Dec. 31, 2011

I want the drivers to be owned by a user, Foo. Whenever the drivers are called by application Duh, I want a program Bar to run after the driver has done its work, since Foo is now running the driver. Is it possible? Anil

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logging kernel panics with netconsole
by chromaticwt zac Dec. 30, 2011

Dec. 30, 2011

my laptop is getting kernel panics often. I have a desktop connected to my internet router via ethernet, and my laptop connected to my router via wifi. how can I log my laptops panics on my desktop? I'm hoping to do this using wifi somehow. I am a newbie, and I know nothing about networking. should I use netconsole? or is there a way for panics to be logged to disk. I really want to find a patch/s to fix these panics, as my laptop freezes with panics 2-4 times a day... thanks, zac

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Check Interface Status
by Rahul Kumar Dec. 30, 2011

Dec. 30, 2011

Hi, I would like to check the interface status (up/down) within linux kernel. Is there any routine (sort of ioctl) to do this. Any code that is already in use in kernel would also be helpful for me. Please let me know.

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[BUG] SIOCSIFFLAGS returns -EIO on SMSC LAN911x
by Javier Martinez Canillas Dec. 30, 2011

Dec. 30, 2011

Hello, We have an issue with the SMSC LAN911x driver with today linux-2.6 [1] executing on an IGEPv2 [2] board using omap2plus_defconfig. When I try to bring up the network interface, the ioctl set interface flags command (SIOCSIFFLAGS) fails returning -EIO: root@igep00x0:~# ifconfig eth0 up ifconfig: SIOCSIFFLAGS: Input/output error But if I execute again it succeeds: root@igep00x0:~# ifconfig eth0 up [ 832.465423] smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 0xdb086000, IRQ: 336 We found that the problem is on the SMSC LAN911x driver (drivers/net/ethernet/smsc/smsc911x.c) net_dev ndo_open function handler smsc911x_open. When the handler is called, it tries to software reset the device by writing a bit to a self-clearing configuration register. According to the data-sheet the hardware clears that bit to notify that the reset was successfully: static int smsc911x_soft_reset(struct smsc911x_data *pdata) { unsigned int timeout; unsigned int temp; /* Reset the LAN911x */ smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_); timeout = 10; do { udelay(10); temp = smsc911x_reg_read(pdata, HW_CFG); } while ((--timeout) && (temp & HW_CFG_SRST_)); if (unlikely(temp & HW_CFG_SRST_)) { SMSC_WARN(pdata, drv, "Failed to complete reset"); return -EIO; } return 0; } The condition temp & HW_CFG_SRST_ is false so the error code -EIO is returned and propagated to user-space. By doing a git bisect we found that this strange behavior exists when the Kconfig tristate compilation condition SMSC_PHY has the value yes to be compiled built-in: SMSC_PHY=y If this config symbol has the value module (m) or not build at all, then bringing up the network interface never fails. Did anyone have the same problem? The problem is really strange to me, especially since we are sure that all the requirements to software reset the device are meet in both cases (with SMSC_PHY compiled built-in and without it) [1]: HEAD on commit 371de6e4e0042adf4f9b54c414154f57414ddd37 drm/i915: Disable RC6 on Sandybridge by default [2]: https://wiki.linaro.org/Boards/Igep Thank you and best regards, -- Javier Martínez Canillas (+34) 682 39 81 69 Barcelona, Spain

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