On Thu, Jan 09, 2020 at 12:30:20AM +0530, Muni Sekhar wrote:
Hi All,
I have module with Xilinx FPGA. It implements UART(s), SPI(s), parallel I/O and interfaces them to the Host CPU via PCI Express bus. I see that my system freezes without capturing the crash dump for certain tests. I debugged this issue and it was tracked down to the ‘readl()’ in interrupt handler code
In ISR, first reads the Interrupt Status register using ‘readl()’ as given below. status = readl(ctrl->reg + INT_STATUS);
And then clears the pending interrupts using ‘writel()’ as given blow. writel(status, ctrl->reg + INT_STATUS);
I've noticed a kernel hang if INT_STATUS register read again after clearing the pending interrupts.
Why would you read that register again after writing to it? And are you sure you are reading/writing the correct size of the irq field? I thought it was a "word" not "long"? But that might depend on your hardware, do you have a pointer to the kernel driver source you are using for all of this? thanks, greg k-h