HI, I am working on linux kernel MMC layer which is responsible for supporting SD/MMC cards on ARM platform. I am stuck with an issue related to TI OMAP driver in this layer. *Background of Problem* - OMAP is not SDHCI compliant In the mmc linux kernel driver stack, most of the drivers are sdhci compilant. All sdhci compliant drivers have a common code which is written in sdhci.c and a specific hardware dependent code which are present is files like tegra-sdhci.c for NVIDIA Tegra and sdhci-esdhc for Freescale iMX. *For NVIDIA Tegra* - http://lxr.free-electrons.com/source/drivers/mmc/host/sdhci-tegra.c *For Freescale iMX* – http://lxr.free-electrons.com/source/drivers/mmc/host/sdhci-esdhc-imx.c Since the present omap_hsmmc driver as of now is not sdhci complaint, it does all these tasks by itself as shown in the below link – http://lxr.free-electrons.com/source/drivers/mmc/host/omap_hsmmc.c *MY OBJECTIVE - MAKE OMAP SDHCI COMPLIANT* I need to get memory mapping of registers right. What I found was that the memory mapping defined in the SDHCI was not same as that of omap. So I wrote to TI but he said the registers are mapping, even the offsets are same. He gave me the example of these two registers from am335x TRM here- http://www.ti.com/lit/ug/spruh73j/spruh73j.pdf
From 18.5.1.10 in AM335x TRM: SD_CMD[31:16] = the command register. *SD_CMD[15:0] = the transfer mode*
From 18.5.1.17 *SD_HCTL[23:16] = Block gap control.*
In the SDHCI spec given here - https://www.sdcard.org/downloads/pls/simplified_specs/archive/partA2_300.pdf these registers are having these memory address/offsets - *Transfer Mode Register (Offset 00Ch)* *Block Count Register (Offset 006h)* I am not able to figure out how these offsets are same. Can someone help me regarding this. Regards, Saket Sinha