Hi,
You didn't mention exactly when you're enabling the data cache. If it's prior to executing the kernel, then your code needs to make sure that the MMU (and hence the data cache) has been disabled prior to running the kernel itself.
The kernel will then turn the MMU, data and instruction caches on as part of its own initialization.
We donot have any bootloader.,so all the necessary initialisations are done using Trace32 cmm script. In this Trace32 script I am making sure that i am turning off MMU before i entering kernel as the dcahe is enable prior to kernel. I could see the following console message( in red ) through early printk -- <5>Linux version 3.1.6-00002-g527439a-dirty (karthik@swaminathan-linuxpc) (gcc version 4.5.3 (Ubuntu/Linaro 4.5.3-7ubuntu1~ppa4) ) #82 Wed Mar 28 10:30:35 EDT 2012 CPU: ARM926EJ-S [+08080C888CPU: TTTTta cache,,,,VVVVnstruction cache 5TEJ), cr=+004444Machine: FFFF6666oooo nstruction cache 5TEJ), cr=+004444<5>Ignoring RAM aaaa000000000000<3>INITRD: 0xxxx22220000<5> lowmem_limit :0x++++Memory policy: ECCCCiiiiled, Data cache wwwweeeekkkky region - disabling initrd *<0>Kernel panic - not syncinggggRRRR::::iiii aaaacccc* isabling initrd [[[[888800002222 wwww____kkkkccccfrom 222200006666]]]]nnnnppppaaaaaaaa [[[[000066662222 wwwwppppaaaaccccfrom 222200002222]]]]nnnniiiiaaaaaaaa [[[888822222222 wwwwiiiiaaaaccccfrom 22226666EEEE]]]]nnnnbbbbkkkkllllbbbb++////0000) [[[[6666EEEE0000 wwwwbbbbkkkkllllbbbb++++////0000rom [[[[6666EEEE0000 wwwwbbbbkkkkllllbbbb++++////0000++++/) [[[[6666EEEE0000 wwwwbbbbkkkkllllbbbb++++////0000++++////++++////rom [[[[6666AAAA04>] (unwllllllll++++////) [[[[6666AAAA0000 wwwwllllllll++++////rom [[[[88882222AAAA wwwwiiiiiiii++++AAAA04>] (unwllllllll++++////) [[[[88882222AAAA wwwwiiiiiiii++++rom [[[[888822220000 wwwwuuuurrrr++++++++AAAA04>] (unwllllllll++++////) [[[[6666CCCC0000 ttttaaaa++++) from [<<<<666644444444((((wwwwuuuurrrr++++++++AAAA04>] (unwllllllll++++////) [[[[666644440000 from 222200000000]]]] 44444444((((wwwwuuuurrrr++++++++AAAA04>] (unwllllllll++++////). We could see control going to panic(shown in bold.). Please let me know how dcahe enabling is resulting in panic., with dcache disabled(CPU_DCACHE_DISABLE = y) everything seems to be OK. On Tue, Mar 27, 2012 at 9:32 PM, Dave Hylands <dhylands@gmail.com> wrote:
Hi Karthiik,
On Tue, Mar 27, 2012 at 5:12 AM, KARTHIK SEKURU <karthik.sekuru@gmail.com> wrote:
Hi,
I'm doing kernel porting to arm926 based FPGA board, very minimal setup. ...snip... If I enable data cache and debug with JTAG, Kernel ends up in ENTRY(__delay).
So you mentioned enabling the data cache. So on the ARM, enabling the data cache means that the MMU has to be enabled.
There is a "rule" that the MMU MUST be off when the kernel starts, or things won't work properly. http://lxr.linux.no/linux+v3.3/Documentation/arm/Booting#L159
You didn't mention exactly when you're enabling the data cache. If it's prior to executing the kernel, then your code needs to make sure that the MMU (and hence the data cache) has been disabled prior to running the kernel itself.
The kernel will then turn the MMU, data and instruction caches on as part of its own initialization.
-- Dave Hylands Shuswap, BC, Canada http://www.davehylands.com