Re: Issue with dcahe enabling.

Using ARM926e-js processor with 128MB SDRAM., Clock-33Mhz

SDRAM Size = 128M

CONFIG_PAGE_OFFSET = 0xc0000000

CONFIG_PHYS_OFFSET= 0x80000000

Kernel Lowmem = 32M including 8M for initramfs (starting from  24M to 32M).

If SDRAM is 128MB why only 32M for lowmem?

This is due to the corruption of the “meminfo” structure.

How is meminfo information being passed? Is it from atags? What is your atags_offset?

Please let me know how dcahe enabling is creating this effect.,as with dcache disabled(CPU_DCACHE_DISABLE = y)  this instruction is replacing the

I am not sure if dcache has anything to do with your problem. -syed