Hi Kosta, I have one more question.I have searched in the source code,but couldn't figure it out. As you mentioned earlier,running ISR in SVC is mainly to make it re entrant,but where its getting enabled again(interrupt) after ARM has been disabled it when an interrupt happens. Could you please give an idea on this. With Regards, Subin K G On Mon, Dec 12, 2011 at 2:23 AM, Konstantin Zertsekel <zertsekel@gmail.com> wrote:
FIQ exception is not implemented in Linux Kernel. Actually, when ARM CPU takes FIQ exception, it branches to 0xffff001c address, which contains the below code from entry-armv.S: vector_fiq: disable_fiq subs pc, lr, #4
Now, disable_fiq not implemented for all the platforms. But, anyway, 'subs pc, lr, #4' returns the CPU to the point where FIQ exception has happened and the system continues to run as usual.
As you said, disable_fiq is empty in OMAP architecture. .macro disable_fiq .endm
So from the above explanation,I can saythat LINUX is not making use of FIQ feature of arm.Am I right?
Absolutely. --- Kosta
-- With Regards Subin Gangadharan I am not afraid and I am also not afraid of being afraid.