On Wed, Jul 11, 2012 at 12:04 PM, Arun KS <getarunks@gmail.com> wrote:
Hello Mulyadi,
On Tue, Jul 10, 2012 at 9:42 PM, Mulyadi Santosa <mulyadi.santosa@gmail.com> wrote:
Hi..
On Tue, Jul 10, 2012 at 6:51 PM, Arun KS <getarunks@gmail.com> wrote:
Hello Experts,
I have a requirement to change __log_buf memory(kernel printk buffer) as non cacheable memory. How can I change the page attributes for changing cache policy to non cacheable?
I just can give short clue. I think somehow you must find its PTE entry...there, IIRC there is page attribute that can be changed to make it uncacheable.
cross check the Intel processor manual for further clarification (if it's indeed x86 arch)
__log_buf size is 512KB and PTE is mapped to a 1MB section. So if I change the attribute for this 1MB section, lot of other stuffs(in this 1MB bss section) will also become non-cachable. Looks like it is not possible unless my __log_buf is 1MB in size. Or I need to create another section like .init, .data, .bss and create 4KB pages(with two levels of Page Tables) instead of 1M section.
My arch is arm-v7
I went ahead and made my __log_buf size to 1MB. But the memory is not aligned to 1MB boundary. Here is what system.map shows. c08ac400 b __warned.32427 c08ac404 b __log_buf c09ac404 B console_set_on_cmdline c09ac408 b idle_notifier c09ac40c B sys_tz so __log_buf resides in two 1M sections in parts and it needs two PTEs. Then I added __aligned__(1024*1024) attribute to __log_buf array. This time compiler error "Error: alignment too large: 15 assumed" But __aligned_(32*1024) is working fine as below c08b84c0 b __warned.32427 c08c0000 b __log_buf c09c0000 B console_set_on_cmdline c09c8000 b idle_notifier c09c8004 B sys_tz Is it not possible to align more than 32KB? Any pointers? Thanks, Arun
Thanks, Arun
-- regards,
Mulyadi Santosa Freelance Linux trainer and consultant
blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com