Hi Greg, On 06/10/19 11:18, Greg KH wrote:
On Sun, Oct 06, 2019 at 12:29:18AM +0200, Luca Ceresoli wrote:
BTW I guess having an FPGA external to the SoC connected via SPI or I2C is not uncommon. Am I wrong?
Not uncommon at all, look at the drivers/fpga/ subsystem for a standard way to access those types of chips with a standard api.
My question was probably ambiguously stated, sorry. drivers/fpga/ has drivers to send a bitstream to an unconfigured FPGA, which uses protocols casted in silicon by FPGA vendors. My question was about the connection between a configured FPGA and the main SoC. This is subject to the fantasy of the FPGA implementer, which explains why there is no specific protocol implemented in mainline: it is usually either a standard bus (typically memory-mapped or PCIe) or a custom protocol over I2C or SPI. I think only DFL is somewhat different, but it doesn't apply to my case since it assumes MMIO, and if I had MMIO I wouldn't have started this thread at all. -- Luca