From a quick look the driver reads / writes the clock wizard IP core's registers and uses device tree bindings to access that part of AXI4 mapped memory. All this implies that you need an hard/soft cpu core inside the FPGA that will run Linux and this driver. The clock wizard IP core will need to be properly instantiated and mapped on the hard / soft cpu's AXI4 interconnect so that the driver can access its registers.
To test the driver I suggest that you buy the cheapest Zynq board that you can find and just build a simple block design in Vivado. The cpu on the FPGA that will run Linux will be the Zynq PS hard cpu core and thus you just need to create a simple block design with the Zynq PS and the clocking wizard IP core. Of-course actually running this involves the preparation of ROM that will contain your FPGA bitsteam with your design and the bootable image of the kernel, i.e you must be familiar with the whole Vivado/SDK flow for embedded designs. Xilinx provides a lot of documentation material on these, it's just a matter of time to read through them and follow the relative simple steps. An alternative is the Zynq Book which covers all these in a very simple fashion that I don't really like but it could be of use by someone inexperienced with FPGAs and particularly the Zynq FPGA devices. http://www.zynqbook.com And for Zynq development boards I recommend the Parallella board which can be bought for ~$125-$250 or the SnickerDoodle board for ~$145-$195. The former is a bit old and besides the FPGA it contains a parallel chip called Epiphany to experiment with parallel programming alongside the Zynq FPGA. The latter is more recent and has a lot of I/O pins if you need them. https://www.parallella.org/buy/ https://www.crowdsupply.com/krtkl/snickerdoodle Elias