Thanks Kosta, I have looked at the code,but it seems 3.0 is slightly different. Anyway your pointers will help me to understanding it better. On Tue, Dec 13, 2011 at 6:52 AM, Konstantin Zertsekel <zertsekel@gmail.com> wrote:
I have one more question.I have searched in the source code,but couldn't figure it out. As you mentioned earlier,running ISR in SVC is mainly to make it re entrant,but where its getting enabled again(interrupt) after ARM has been disabled it when an interrupt happens. Could you please give an idea on this.
Please take a look at handle_IRQ_event in kernel/irq/handle.c:
irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action) { irqreturn_t ret, retval = IRQ_NONE; unsigned int status = 0;
if (!(action->flags & IRQF_DISABLED)) local_irq_enable_in_hardirq(); <--- !!!!!!!!!!!!!!!!!!!!!!!!!
... }
It is called from kernel/irq/chip.c file for every type of IRQ interrupt (simple IRQ, level IRQ, enge IRQ and percpu IRQ).
Now, local_irq_enable_in_hardirq is defined in inlude/linux/interrupt.h:
#ifdef CONFIG_LOCKDEP # define local_irq_enable_in_hardirq() do { } while (0) #else # define local_irq_enable_in_hardirq() local_irq_enable() #endif
Now, local_irq_enable is defined in include/linux/irqflags.h:
#define local_irq_enable() \ do { trace_hardirqs_on(); raw_local_irq_enable(); } while (0) And, at last, raw_local_irq_enable is defined in arch/arm/include/asm/irqflags.h:
#define raw_local_irq_enable() \ ({ \ unsigned long temp; \ __asm__ __volatile__( \ "mrs %0, cpsr @ local_irq_enable\n" \ " bic %0, %0, #128\n" \ " msr cpsr_c, %0" \ : "=r" (temp) \ : \ : "memory", "cc"); \ })
This last macro essentially clears the I (big i) bit in CPSR register - this enables IRQ exceptions.
Hope, it helps. --- Kosta
-- With Regards Subin Gangadharan I am not afraid and I am also not afraid of being afraid.