Following the text at https://www.kernel.org/doc/Documentation/DMA-API.txt a few inlined questions Part Ia - Using large dma-coherent buffers ------------------------------------------ void * dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) Consistent memory is memory for which a write by either the device or the processor can immediately be read by the processor or device without having to worry about caching effects. (You may however need to make sure to flush the processor's write buffers before telling devices to read that memory.) Q1. Is it safe to assume that the area allocated is cacheable ? As the last line state that flushing is required Q1a. Does this API allocate memory from lower 16MB which is considered DMA safe. dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction direction) Maps a piece of processor virtual memory so it can be accessed by the device and returns the physical handle of the memory. The direction for both api's may be converted freely by casting. However the dma_ API uses a strongly typed enumerator for its direction: DMA_NONE no direction (used for debugging) DMA_TO_DEVICE data is going from the memory to the device DMA_FROM_DEVICE data is coming from the device to the memory DMA_BIDIRECTIONAL direction isn't known Q2. Does the DMA_XXX options direct change of Page Attributes for the VA=>PA mapping. Say DMA_TO_DEVICE would mark the area as non-cacheable ? -- -mj