Hello Krishna, On Wed, Sep 7, 2016 at 6:42 AM, Er Krishna <erkrishna@gmail.com> wrote:
Hi All,
I am asking below question for understanding. Pls help me to understand this:
1. How does APIC schedule interrupt on particular core ? How does Apic takes a decision that first few interrupt will be schedule on Core 0 and remaining for load balancing will be schedule on different core ? What are the advantage of scheduling interrupt always on core 0 w.r.t Cache hot and all ?
I m not familiar with APIC, will try to answer you question w.r.t GIC used on ARM cores. Interrupt controllers usually have AFFINITY mask registers. When an interrupt arrives and affinity mask of this irq show more than one cpu, Interrupt controllers trigger interrupt on all the valid cpus(w.r.t mask value). Which ever cpu turns up first and acknowledge, get the chance to serve the interrupt. It is a software design decision to choose whether to route all the interrupts to one cpu or multiple cpus. One major advantage of ISR running on same cpu is because of hot instruction cache. Lets say one interrupt is firing so frequently, if they hit on the same cpu, the instruction are highly probable to be cached. This benefit is present for data caches aswell, but there are advance hardware mechanism(scu and CCI for arm) to move data from cache across cpus and clusters where as instruction caches doesn't.
2. Is it possible that incoming interrupt can be scheduled on particular core rather than core 0 ? What is the configuration option or api is available for that inside kernel or in user space ?
You can set interrupt affinity mask of an interrupt from user space. May be this is also interesting for you, https://linux.die.net/man/1/irqbalance Regards, Arun
Thanks, Krishna
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