November 2021 - kernelnewbies@kernelnewbies.org

Re: MTD: How to get actual image size from MTD partition
by Pintu Agarwal Nov. 12, 2021

Nov. 12, 2021

On Thu, 29 Jul 2021 at 17:33, Ezequiel Garcia <ezequiel(a)vanguardiasur.com.ar> wrote: > > On Thu, 29 Jul 2021 at 08:45, Richard Weinberger <richard(a)nod.at> wrote: > > > > Ezequiel, > > > > ----- Ursprüngliche Mail ----- > > > [snip] > > > > > > Ouch, so surprised that after all these years someone is doing squashfs/mtdblock > > > instead of using ubiblock :-) > > > > > > Can we patch either Kconfig or add some warn_once on mtdblock > > > usage, suggesting to use ubiblock instead? > > > > a hint in Kconfig makes IMHO sense. Do you want to send a patch? > > A warning is too much since on some tiny embedded system with NOR flash mtdblock is still > > a good choice. > > ubiblock is mostly useful for NAND flash. > > > > > I remember there was still some use case(s) for mtdblock but I can't remember > > > now what was it, perhaps we should document the expectations? > > > (Is that for JFFS2 to mount?) > > > > a long time ago mount didn't accept character devices, so you had to pass mtdblockX to mount > > JFFS2. > > This limitation is gone. > > > > OK, let me try to cook a patch for you. > Dear Eze and Richard, First of all, thank you so much for all your replies so far. Sorry, I have limited knowledge about NAND, MTD, UBI layers, but my current work involves all these so I am here. But I will surely share this information to our internal team about using ubiblock instead of mtdblock. However, I still fail to understand the problem and consequences of using mtdblock for rootfs instead of ubiblock. Last time, for my squashfs test, when I tried to replace the command line with ubiblock, I could not see any difference. How to visibly see the difference so that I can easily understand and explain the difference internally? Or, is there a document available somewhere to highlight the difference between the two? BTW, we have few raw nand partitions and few ubi volumes [including rootfs(squashfs), data(ubifs, rw)] So, I guess we should use ubiblock for all ubi volumes? Regarding Kconfig, I have few opinions. Yes, adding more description in Kconfig is a good choice. But I see that most of the time these kernel config options remains (as default) and platform developers never cares about the description. So, how to better create awareness among them, not to make these mistakes? One option is to capture these details as part of Kernel documentation. Right now when I search I could not find anything. Another option is to add a few (critical) warnings in kernel bootup logs to give some hint to the developer that there is probably something wrong. This will directly be visible to all and some developers will not like to ignore it. Or, maybe adding both options is also good. Thanks, Pintu

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Question about "barrier()" in the SLUB's fast path
by Wonhyuk Yang Nov. 12, 2021

Nov. 12, 2021

Hi, Recently, I had difficulty understanding the meaning of the barrier() in the slab_alloc_node(). The comments are written like this. /* * Irqless object alloc/free algorithm used here depends on sequence * of fetching cpu_slab's data. tid should be fetched before anything * on c to guarantee that object and page associated with previous tid * won't be used with current tid. If we fetch tid first, object and * page could be one associated with next tid and our alloc/free * request will be failed. In this case, we will retry. So, no problem. */ barrier(); Even if we don't fetch tid first, don't we try again by this_cpu_cmpxchg_double? I'd really appreciate it if you let me know what I missed!

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loading a simple hypervisor(just prints Hello World) before the linux kernel
by Mushahid Hussain Nov. 11, 2021

Nov. 11, 2021

Hi, I'm trying to learn about the Linux kernel and the bare metal world on raspberry pi 4. After writing a simple kernel, which would print Hello World to UART, I tried to write Hello World using two different binaries loaded at two different addresses(and on two different exception levels!(EL2 and EL1). el2-kernel.img - this just prints Hello to UART. el1-kernel.img - this just prints World to UART. I used the following configuration on rpi4, to load both binaries on rpi4. kernel=el2-kernel.img initramfs el1-kernel.img 0x400000 In the el2-kernel.img, I wrote a function which would jump from any exception level to EL1 at 0x400000. I have successfully done so. I can see the Hello World printed to UART by two different binaries. What I cannot do is to jump from a binary(let's call it a simple hypervisor, which prints Hello World) at EL2 to the standard linux kernel at El1. How would I be able to do so? I have tried the same with standard linux kernel and "kept" dtb address in x0, so it can used by the linux kernel. My code for the simple hypervisor: https://github.com/SikkiLadho/Leo

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correct source tree to make contributions to Linux thermal framework
by Balakrishnan, Anand Nov. 10, 2021

Nov. 10, 2021

Hello Developers, At our company, we maintain an internal thermal framework patch. We are exploring the option to up-stream this patch so we don't have to keep porting this from one Kernel version to the other. Thermal framework code resides here: https://elixir.bootlin.com/linux/latest/source/drivers/thermal? What is the correct source tree we should use from https://git.kernel.org/?? Thanks, Anand

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Will two processes each holding a given spin lock be seen as ordered by a third process not holding that lock?
by Zhang Zeren Nov. 10, 2021

Nov. 10, 2021

Hi all, In tools/memory-model, there are two litmus tests named *ISA2+pooncelock+pooncelock+pombonce *and *Z6.0+pooncelock+pooncelock+pombonce. *As far as I understand it, these two files test exactly the same thing: will two processes each holding a given spin lock be seen as ordered by a third process not holding that lock? However, ISA2+pooncelock+pooncelock+pombonce says YES, and Z6.0+pooncelock+pooncelock+pombonce says MAYBE NOT. I also read a patch about ISA2+pooncelock+pooncelock+pombonce ( https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/too…) If I get it right, is Z6.0+pooncelock+pooncelock+pombonce out of date? Thanks, Zhang Zeren

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Kernel module that shuts down the device
by Drew Abbott Nov. 9, 2021

Nov. 9, 2021

Hi all, I am working on a kernel module that should shut down the device when USB is unplugged. I make a call to kernel_power_off(), but I see that it gets stuck trying to call blocking_notifier_call_chain(&reboot_notifier_list, (state == SYSTEM_HALT) ? SYS_HALT : SYS_POWER_OFF, NULL); in kernel_shutdown_prepare(). There is currently another driver that has the same function, and shuts down the device by calling kernel_power_off() successfully. I have tried adding prints in blocking_notifier_call_chain, but then the kernel log is flooded with calls and I can't really see what is happening. Does anyone have any insight into why my call to kernel_power_off() is hanging? Thanks, Drew

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litmus test for multicopy atomic
by Zhang Zeren Nov. 5, 2021

Nov. 5, 2021

Hi, all I read a test named SB+rfionceonce-poonceonces in tools/memory-model/litmus-tests like this > > P0(int *x, int *y) > { > int r1; > int r2; > > WRITE_ONCE(*x, 1); > r1 = READ_ONCE(*x); > r2 = READ_ONCE(*y); > } > > P1(int *x, int *y) > { > int r3; > int r4; > > WRITE_ONCE(*y, 1); > r3 = READ_ONCE(*y); > r4 = READ_ONCE(*x); > } > > locations [0:r1; 1:r3; x; y] (* Debug aid: Print things not in "exists". *) > exists (0:r2=0 /\ 1:r4=0) > The comment says > This litmus test demonstrates that LKMM is not fully multicopy atomic. I understand why 0:r2=0 /\ 1:r4=0 is possible: r2 = READ_ONCE(*y); executes before WRITE_ONCE(*x, 1); in P0 and r4 = READ_ONCE(*x); executes before WRITE_ONCE(*y, 1); in P1. But I don't understand why this test is suffice to "demonstrates that LKMM is not fully multicopy atomic". I got the definition of multicopy atomic in ARM's documentation, which says > in a multiprocessing system, if one observer observes a write to memory > because of a store-release operation, then all observers observe it. > As far as I understand it, this litmus test wants to know if P0 and P1 can observe the value change of x and y at the same time. More specifically, after P1 executed WRITE_ONCE(*x, 1) and r1 got new value 1, we want to know if P1 can also observe the new value of x. But there is no guarantee that r4 = READ_ONCE(*x); has been executed. Given that "All store-release operations are multi-copy atomic" in Arm, I designed a assembly code version of this litmus test, like this > { > 0:X1=x; 0:X4=y; > 1:X1=y; 1:X4=x; > } > P0 | P1 ; > MOV W0,#1 | MOV W0,#1 ; > STLR W0,[X1] | STLR W0,[X1] ; > LDR W2,[X1] | LDR W2,[X1] ; > LDR W3,[X4] | LDR W3,[X4] ; > locations [0:X2; 1:X2; x; y] > exists (0:X3=0 /\ 1:X3=0) > If STLR provide multicopy atomic, and this test can confirm it, we should't get the (0:X3=0 /\ 1:X3=0) and the test result show that (0:X3=0 /\ 1:X3=0) do exists. So, why this test can "demonstrates that LKMM is not fully multicopy atomic"? And did I misunderstand something? Thanks in advance. Zhang Zeren

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Loading a simple "kernel" at the address other than default on Raspberry Pi 4
by Mushahid Hussain Nov. 4, 2021

Nov. 4, 2021

Hi, I have written a simple kernel which prints Hello World to UART. The simple kernel works successfully and prints Hello World to UART, if I load it at 0x80000, which is the default load address for the 64-bit kernel. There's a configuration(config.txt)[1] kernel_address on Raspberry Pi 4 but whenever I change the load address by even 1 byte, the simple kernel would not run. It is only able to run at 0x80000. I tried to find the entry address of the standard kernel for raspberry pi[2]. I have trusted firmware-A[3] on my Raspberry Pi, which prints the load address before loading the standard kernel. Entry address for the standard kernel is always 0x200000! Even if I manually change the load address in the raspberry pi configuration, the standard kernel is always loaded at 0x200000!. How is the standard kernel being loaded at 0x200000, but my simple kernel cannot be loaded at any address except for the default address(0x80000)? [1] https://github.com/raspberrypi/documentation/blob/develop/documentation/asc… [2] https://github.com/raspberrypi/linux [3] https://www.trustedfirmware.org/projects/tf-a/

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In the device tree, what does multiple cpu nodes mean inside 'cpus' node without the wrapping 'cpu-map' node?
by Chan Kim Nov. 4, 2021

Nov. 4, 2021

Hello all, There is something I can't understand clearly about the device tree's cpu topology so I ask it here. In Documentation/devicetree/bindings/cpu/cpu-topology.txt, it says abput cpu-map node, - cpu-map node Usage: Optional - On SMP systems provide CPUs topology to the OS. Uniprocessor systems do not require a topology description and therefore should not define a cpu-map node. Description: The cpu-map node is just a container node where its subnodes describe the CPU topology. Node name must be "cpu-map". The cpu-map node's parent node must be the cpus node. The cpu-map node's child nodes can be: - one or more cluster nodes or - one or more socket nodes in a multi-socket system Any other configuration is considered invalid. And the arch/arm64/boot/dts/arm/juno.dts files shows the usage of this cpu-map node. cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&A57_0>; }; core1 { cpu = <&A57_1>; }; }; cluster1 { core0 { cpu = <&A53_0>; }; core1 { cpu = <&A53_1>; }; core2 { cpu = <&A53_2>; }; core3 { cpu = <&A53_3>; }; }; }; But in arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts, cpus { #address-cells = <2>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0 0>; next-level-cache = <&L2_0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0 1>; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; }; }; So, uni-processor system should not define a cpu-map node and the above vexpress-v2f-1xv7-ca53x2 fpga tile has this multiple cpus directly inside the cpus node(without wrapping with cpu-map node). So even though it is not uni-processor system, it doesn't have cpu-map node, Just cpu nodes. What does it mean? Does it mean this system doesn't support SMP? Or, I can use style without violation? Any comment/explanation will be very much appreciated. Thank you! Chan Kim

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How can I use id and schema page of a yaml file in the devicetree bindings document?
by Chan Kim Nov. 2, 2021

Nov. 2, 2021

Hello all In the file Documentation/devicetree/bindings/arm/primecell.yaml, I see in the beginning, # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- $id: http://devicetree.org/schemas/arm/primecell.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Primecell Peripherals following the link in the id and schema just leads me to https://www.devicetree.org/schema/# and it says "These are not the schemas you are looking for." How can I open the links and use them? Thanks a lot! Regards, Chan Kim

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