arm64: Question about barriers with the mmu off
vvghjk1234 at gmail.com
Tue Nov 17 19:53:11 EST 2020
On Tue, Nov 17, 2020 at 3:25 PM Valdis Klētnieks
<valdis.kletnieks at vt.edu> wrote:
> > > > > dc ivac,x1 // invalidate a cache line that's probably OK
> > > > > str w0,[x1 // and now we do a store that leaves a possibly stale cache line
> > Could you explain me why the store still leaves stale cache?
> > We invalidated the cacheline and store will not make footprint in the cache.
> There's a race condition...
> Invalidate the cache line.... then another CPU manages to fetch the cache line.
> and then we do a store that doesn't update the cache - and the other CPU
> is still looking at the old data.
Oh, I didn't consider that another cpu read with cacheable.
Now I understand why the barrier is here.
Thank you for your help.
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