arm64: Question about barriers with the mmu off
vvghjk1234 at gmail.com
Mon Nov 16 06:58:52 EST 2020
Hi, I have a question about dmb barriers in arm64's head.S.
In the head.S, I could see the pattern below several times.
str w0, [x1]
dc ivac, x1 // Invalidate potentially stale cache line
I found that,
Commit(fix cache flushing and barriers in set_cpu_boot_mode_flag)
explained the code.
> This patch reworks the broken flushing code so that we:
> (1) Use a DMB to order the strongly-ordered write of the cacheline
> against the subsequent cache-maintenance operation (by-VA
> operations only hazard against normal, cacheable accesses).
> (2) Use a single dc ivac instruction to invalidate any clean lines
> containing a stale copy of the line after it has been updated.
> Use a DMB to order the strongly-> ordered write of the cacheline
But I can't understand why the store operation should precede the
Is there any problem, if the dc operation precedes the store operation?
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