Memory barrier

[Vladimir Murzin]

Hi,

In my opinion it is not correct to say "make order on current CPU" in
case of SMP. Actually, we cope with shared resource here - memory, and
observes for that resource - CPUs.

As soon as CPU is asked to make a barrier (with some sort of
instruction) access to shared resource is ordered among all of
observers. So, in case of SMP we have to protect shared resource with
"hardware" memory barriers. In case of UP, memory is not shared, so,
generally, we have to take care that memory access won't be optimized
by compiler.

P.S.
Sorry for digging this thread.

Best wishes
Vladimir Murzin

On 12/9/11, 卜弋天 <buyit at live.cn> wrote:
>
> Hi :
>
>       if you write code as below:
>
> golbal int in1=0,int2=0;
>
> cpu1:                     cpu2:
>
> int1 = 1;                 b= int2;
> smp_wmb()
> int2 = 2;                 a = in1;
>
> cpu2 may get the result: b==2 & a==0 , which means although cpu1 set int1=1
> before int2=2, there is no garentee for cpu2 to perceive int1 before int2.
> you must add smp_rmb() inside cpu2 to prevent this.
>
> two cpus must cooperate to acheive the sequence memory order.
>
>
>
>
>
>> Date: Fri, 9 Dec 2011 14:14:37 +0530
>> Subject: Re: Memory barrier
>> From: trisha1march at gmail.com
>> To: buyit at live.cn
>> CC: kernelnewbies at kernelnewbies.org
>>
>> I will add more info here:
>> smp_mb()
>> Similar to mb(), but only guarantees ordering between cores/processors
>> within an SMP system. All memory accesses before the smp_mb() will be
>> visible to all cores within the SMP system before any accesses after
>> the smp_mb().
>> smp_rmb()
>> Like smp_mb(), but only guarantees ordering between read accesses.
>> smp_wmb()
>> Like smp_mb(), but only guarantees ordering between write accesses.
>>
>> So these made me total confuse .
>>
>> Thanks
>>
>> 2011/12/9 trisha yad <trisha1march at gmail.com>:
>> > Thanks,
>> >
>> > I got bit confuse with below statement:
>> > This is from paper Memory access ordering Part 2
>> > SMP conditional barriers
>> > The SMP conditional barriers are used to ensure a consistent view of
>> > memory between different cores within a cache coherent SMP system.
>> > When compiling a kernel without CONFIG_SMP, all SMP barriers are
>> > converted into plain compiler barriers.
>> >
>> > 2011/12/9 卜弋天 <buyit at live.cn>:
>> >> Hi :
>> >>
>> >> memory barriers can not make order on other cpus, only the current
>> >> cpu's order will be promised.
>> >>
>> >>
>> >>
>> >>> Date: Fri, 9 Dec 2011 12:54:40 +0530
>> >>> Subject: Memory barrier
>> >>> From: trisha1march at gmail.com
>> >>> To: Kernelnewbies at kernelnewbies.org
>> >>
>> >>>
>> >>> Hi All,
>> >>>
>> >>> I need small clarification on memory barrier.
>> >>> #define smp_mb() mb()
>> >>> #define smp_rmb() rmb()
>> >>> #define smp_wmb() wmb()
>> >>> In case of SMP:
>> >>> is smp_mb() or smp_rmb() make order on current CPU or all cpu's
>> >>>
>> >>> Thanks
>> >>>
>> >>> _______________________________________________
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