arm64: Question about barriers with the mmu off

[Valdis Kl=?utf-8?Q?=c4=93?=tnieks]

On Tue, 17 Nov 2020 14:08:02 +0900, Wonhyuk Yang said:

> > > > dc ivac,x1   // invalidate a cache line that's probably OK
> > > > str w0,[x1   // and now we do a store that leaves a possibly stale cache line

> Could you explain me why the store still leaves stale cache?
> We invalidated the cacheline and store will not make footprint in the cache.

There's a race condition...

Invalidate the cache line....  then another CPU manages to fetch the cache line.
and then we do a store that doesn't update the cache - and the other CPU
is still looking at the old data.

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