Self modifying code in ARM 11 architectures
Hi All, I am no success in booting up the ARM1176 processor with the linux-2.6.32 kernel. While googling about the ARM Harvard architecture, I came to know that we have to flush/invalidate the D-Cache and I-Cache when using the self modifying codes. So here my questions/doubts : 1) Is'nt it the kernel itself is self modifying code with lots of function pointers ? If yes, how is synchronization b/w d-cache and i-cache handled in the kernel ? 2) Can this be the reason for the kernel not booting for me ? Because If i disable the I-Cache in the config, then the kernel boots up without any issues. Any pointers on this will be of great help. Thanks & Best Regards Ashok
Hi... On Tue, May 24, 2011 at 17:15, Ashok Babu <ashok3d@gmail.com> wrote:
So here my questions/doubts : 1) Is'nt it the kernel itself is self modifying code with lots of function pointers ?
AFAIK, yes there are many.. however, some of them, even in the form of pointer assignment, are rarely changing. But if it is changing, for sure cache needs to be flushed/invalidated. This is especially true in SMP environment ( and don't forget memory barrier....) -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com
Hi! On 10:55 Wed 25 May , Mulyadi Santosa wrote:
Hi...
On Tue, May 24, 2011 at 17:15, Ashok Babu <ashok3d@gmail.com> wrote:
So here my questions/doubts : 1) Is'nt it the kernel itself is self modifying code with lots of function pointers ?
AFAIK, yes there are many.. however, some of them, even in the form of pointer assignment, are rarely changing.
But if it is changing, for sure cache needs to be flushed/invalidated. This is especially true in SMP environment ( and don't forget memory barrier....)
This sounds like a very interesting arch to me. I would very much like to see any code which does cache flushing when changing a function pointer. In the mean time, let us assume that function pointers are data, not code. ;-) Then, you still have to think about concurrency, but not about cache flushing. What could cause trouble: - http://gcc.gnu.org/onlinedocs/gcc/Nested-Functions.html - This requires an executeable stack - never tested whether kernel stacks are executable. No idea if something makes them executable. - Assembly code in arch/ , like the tracing framework. - ??? -Michi -- programing a layer 3+4 network protocol for mesh networks see http://michaelblizek.twilightparadox.com
Hi Michi... On Wed, May 25, 2011 at 22:18, Michael Blizek <michi1@michaelblizek.twilightparadox.com> wrote:
This sounds like a very interesting arch to me. I would very much like to see any code which does cache flushing when changing a function pointer. In the mean time, let us assume that function pointers are data, not code. ;-) Then, you still have to think about concurrency, but not about cache flushing.
I think, changing function pointer assignment is only needed in SMP environment and when we see a chance that that code is executed by more than one concurrent code path. Other than that, in x86, i think it's not needed. And thanks for x86 strict memory ordering, we're not burdened with too much memory barrier. CMIIW here people... -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com
On Tue, May 24, 2011 at 6:15 PM, Ashok Babu <ashok3d@gmail.com> wrote:
Hi All,
I am no success in booting up the ARM1176 processor with the linux-2.6.32 kernel.
While googling about the ARM Harvard architecture, I came to know that we have to flush/invalidate the D-Cache and I-Cache when using the self modifying codes.
So here my questions/doubts : 1) Is'nt it the kernel itself is self modifying code with lots of function pointers ? If yes, how is synchronization b/w d-cache and i-cache handled in the kernel ? 2) Can this be the reason for the kernel not booting for me ? Because If i disable the I-Cache in the config, then the kernel boots up without any issues.
Any pointers on this will be of great help.
Here:
http://blogs.arm.com/software-enablement/141-caches-and-self-modifying-code/ read the part on "The Solution" - it describe function pointer on a register, and what u are supposed to do with cache transfer. (java is full of JIT compilation) <http://blogs.arm.com/software-enablement/141-caches-and-self-modifying-code/>
Thanks & Best Regards Ashok
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-- Regards, Peter Teoh
On Thu, May 26, 2011 at 12:28 AM, Peter Teoh <htmldeveloper@gmail.com> wrote:
On Tue, May 24, 2011 at 6:15 PM, Ashok Babu <ashok3d@gmail.com> wrote:
Hi All, I am no success in booting up the ARM1176 processor with the linux-2.6.32 kernel. While googling about the ARM Harvard architecture, I came to know that we have to flush/invalidate the D-Cache and I-Cache when using the self modifying codes. So here my questions/doubts : 1) Is'nt it the kernel itself is self modifying code with lots of function pointers ? If yes, how is synchronization b/w d-cache and i-cache handled in the kernel ? 2) Can this be the reason for the kernel not booting for me ? Because If i disable the I-Cache in the config, then the kernel boots up without any issues. Any pointers on this will be of great help.
Here: http://blogs.arm.com/software-enablement/141-caches-and-self-modifying-code/
Based on the URL above (where it described to disable I cache to execute self-modified codes), and your observation in (2), I guessed that the behavior is correct. During bootup, linux kernel actually unzip itself, and execute into the unzipped image. And so during this time, the I-cache have to be disabled in order to bring the instruction in from the external memory.
participants (4)
-
Ashok Babu -
Michael Blizek -
Mulyadi Santosa -
Peter Teoh