Question on Alignment requiremnet
Hi All, I have some doubts on the alignment requirement.It would be really helpful,if someone can shed some light on this. Why there are so many different types of alignment like 4 byte, 8 byte,16 byte ?.My exact question is, in a 32 bit machine(I assume processor reads data in 4 bytes),how 16 byte alignment makes different from 4 byte alignment ?.How this will influence the processor performance ?. - With Regards Subin Gangadharan Everything should be made as simple as possible,but not simpler.
On Sat, Aug 6, 2011 at 23:59, subin gangadharan <subingangadharan@gmail.com> wrote:
Hi All, I have some doubts on the alignment requirement.It would be really helpful,if someone can shed some light on this. Why there are so many different types of alignment like 4 byte, 8 byte,16 byte ?.My exact question is, in a 32 bit machine(I assume processor reads data in 4 bytes),how 16 byte alignment makes different from 4 byte alignment ?.How this will influence the processor performance ?.
personal guess: cache line alignment? ... so the data all can be read in one read swipe..... or in other hand, if several data has different access type (some are read only, the rest are read/write), then by aligning them to different cache line, they won't interfere to each other...since AFAIK a write to even one bit in a cache line will update the whole cache line. Other data in the same cache line will stay, they will be just rewritten AFAIK. I hope my guess is right :) -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com
On Sat, Aug 6, 2011 at 10:56 AM, Mulyadi Santosa <mulyadi.santosa@gmail.com>wrote:
On Sat, Aug 6, 2011 at 23:59, subin gangadharan <subingangadharan@gmail.com> wrote:
Hi All, I have some doubts on the alignment requirement.It would be really helpful,if someone can shed some light on this. Why there are so many different types of alignment like 4 byte, 8 byte,16 byte ?.My exact question is, in a 32 bit machine(I assume processor reads data in 4 bytes),how 16 byte alignment makes different from 4 byte alignment ?.How this will influence the processor performance ?.
personal guess: cache line alignment?
... so the data all can be read in one read swipe.....
or in other hand, if several data has different access type (some are read only, the rest are read/write), then by aligning them to different cache line, they won't interfere to each other...since AFAIK a write to even one bit in a cache line will update the whole cache line. Other data in the same cache line will stay, they will be just rewritten AFAIK.
I hope my guess is right :)
Thanks for your quick reply.I have one more question. So in case of processor with read/write granularity of 4 byte access,just for understanding purpose imagine it's with out cache.So in that case any difference is there between 4byte and other 8byte,16 byte alignment.
-- regards,
Mulyadi Santosa Freelance Linux trainer and consultant
blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com
-- With Regards Subin Gangadharan Everything should be made as simple as possible,but not simpler.
Hi Subin... On Sun, Aug 7, 2011 at 02:01, subin gangadharan <subingangadharan@gmail.com> wrote:
Thanks for your quick reply.I have one more question. So in case of processor with read/write granularity of 4 byte access,just for understanding purpose imagine it's with out cache.So in that case any difference is there between 4byte and other 8byte,16 byte alignment.
Sorry, I have no idea about that so far... PS: the best I can think beside data bus alignment, cache alignment...is probably page alignment. -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com
On Aug 6, 2011 1:57 PM, "Mulyadi Santosa" <mulyadi.santosa@gmail.com> wrote:
On Sat, Aug 6, 2011 at 23:59, subin gangadharan <subingangadharan@gmail.com> wrote:
Hi All, I have some doubts on the alignment requirement.It would be really helpful,if someone can shed some light on this. Why there are so many different types of alignment like 4 byte, 8
byte,16
byte ?.My exact question is, in a 32 bit machine(I assume processor reads data in 4 bytes),how 16 byte alignment makes different from 4 byte alignment ?.How this will influence the processor performance ?.
personal guess: cache line alignment?
... so the data all can be read in one read swipe.....
or in other hand, if several data has different access type (some are read only, the rest are read/write), then by aligning them to different cache line, they won't interfere to each other...since AFAIK a write to even one bit in a cache line will update the whole cache line. Other data in the same cache line will stay, they will be just rewritten AFAIK.
I hope my guess is right :)
Too complex I think. Don't try to think so hard. ;-) Most cpu's offer an atomic test_and_set instruction. It is used to write busy loop semaphore code like. While (test_and_set(flag) == false); # coded in assembly Normally that busy loops until flag initially has a value of zero during the test and the test changes it to a one. But if test_and_set always fails due lack of alignment, that loop will never finish. Greg
On Sun, Aug 7, 2011 at 5:22 AM, Greg Freemyer <greg.freemyer@gmail.com>wrote:
On Aug 6, 2011 1:57 PM, "Mulyadi Santosa" <mulyadi.santosa@gmail.com> wrote:
On Sat, Aug 6, 2011 at 23:59, subin gangadharan <subingangadharan@gmail.com> wrote:
Hi All, I have some doubts on the alignment requirement.It would be really helpful,if someone can shed some light on this. Why there are so many different types of alignment like 4 byte, 8
byte,16
byte ?.My exact question is, in a 32 bit machine(I assume processor reads data in 4 bytes),how 16 byte alignment makes different from 4 byte alignment ?.How this will influence the processor performance ?.
personal guess: cache line alignment?
... so the data all can be read in one read swipe.....
or in other hand, if several data has different access type (some are read only, the rest are read/write), then by aligning them to different cache line, they won't interfere to each other...since AFAIK a write to even one bit in a cache line will update the whole cache line. Other data in the same cache line will stay, they will be just rewritten AFAIK.
I hope my guess is right :)
Too complex I think. Don't try to think so hard. ;-)
Most cpu's offer an atomic test_and_set instruction.
It is used to write busy loop semaphore code like.
While (test_and_set(flag) == false); # coded in assembly
Normally that busy loops until flag initially has a value of zero during the test and the test changes it to a one.
But if test_and_set always fails due lack of alignment, that loop will never finish.
Greg
Thank you guys for helping me to clear out the doubts. -- With Regards Subin Gangadharan Everything should be made as simple as possible,but not simpler.
participants (3)
-
Greg Freemyer -
Mulyadi Santosa -
subin gangadharan