According to 

Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3B:
System Programming Guide, Part 2

for 64 bit machines:

On processors that support Intel 64 architecture, the base-address fields for FS,
GS, GDTR, IDTR, and TR must contain canonical addresses.
Look for definition of canonical addresses here:
http://en.wikipedia.org/wiki/X86-64


According to this book all addresses in GDTR, LDTR and IDTR are linear addresses
http://books.google.co.uk/books?id=l8QPUGuElFwC&pg=SA7-PA15&lpg=SA7-PA15&dq=GDTR+32+bit&source=bl&ots=4rS-pTNmaE&sig=CasnhDIFc9pVr0fsAlNqAod-xFc&hl=en&sa=X&ei=vRoiUZXDAojK0QXf8IHYBA&ved=0CEgQ6AEwBQ#v=onepage&q=GDTR%2032%20bit&f=false

Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3A:
System Programming Guide, Part 1
page 65

The linear address of the base of the GDT is contained in the GDT register (GDTR);
the linear address of the LDT is contained in the LDT register (LDTR).


However for 32 bit registers, this document provides some details in protected mode:

http://home.swipnet.se/smaffy/asm/info/PMODEDetailedApproach.txt