<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta http-equiv=Content-Type content="text/html; charset=us-ascii"><meta name=Generator content="Microsoft Word 15 (filtered medium)"><style><!--
/* Font Definitions */
@font-face
{font-family:Gulim;
panose-1:2 11 6 0 0 1 1 1 1 1;}
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Gulim;
panose-1:2 11 6 0 0 1 1 1 1 1;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0cm;
margin-bottom:.0001pt;
text-align:justify;
text-justify:inter-ideograph;
text-autospace:none;
word-break:break-hangul;
font-size:10.0pt;
font-family:"Malgun Gothic";}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:#0563C1;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:#954F72;
text-decoration:underline;}
p.MsoPlainText, li.MsoPlainText, div.MsoPlainText
{mso-style-priority:99;
mso-style-link:"\AE00\C790\B9CC Char";
margin:0cm;
margin-bottom:.0001pt;
text-autospace:none;
word-break:break-hangul;
font-size:10.0pt;
font-family:"Courier New";}
span.EmailStyle17
{mso-style-type:personal;
font-family:"Malgun Gothic";
color:windowtext;}
span.Char
{mso-style-name:"\AE00\C790\B9CC Char";
mso-style-priority:99;
mso-style-link:\AE00\C790\B9CC;
font-family:"Courier New";}
.MsoChpDefault
{mso-style-type:export-only;
font-family:"Malgun Gothic";}
/* Page Definitions */
@page WordSection1
{size:612.0pt 792.0pt;
margin:3.0cm 72.0pt 72.0pt 72.0pt;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]--></head><body lang=KO link="#0563C1" vlink="#954F72"><div class=WordSection1><p class=MsoPlainText><span lang=EN-US>Hello all,<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>There is something I can’t understand clearly about the device tree’s cpu topology so I ask it here.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>In Documentation/devicetree/bindings/cpu/cpu-topology.txt, it says abput cpu-map node, <o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText style='text-indent:20.0pt'><span lang=EN-US>- cpu-map node<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> Usage: Optional - On SMP systems provide CPUs topology to the OS.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> Uniprocessor systems do not require a topology<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> description and therefore should not define a<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu-map node.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> Description: The cpu-map node is just a container node where its<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> subnodes describe the CPU topology.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> Node name must be "cpu-map".<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> The cpu-map node's parent node must be the cpus node.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> The cpu-map node's child nodes can be:<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> - one or more cluster nodes or<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> - one or more socket nodes in a multi-socket system<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> Any other configuration is considered invalid.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>And the arch/arm64/boot/dts/arm/juno.dts files shows the usage of this cpu-map node.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText style='text-indent:20.0pt'><span lang=EN-US>cpus {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> #address-cells = <2>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> #size-cells = <0>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu-map {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cluster0 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> core0 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu = <&A57_0>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> core1 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu = <&A57_1>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> cluster1 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> core0 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu = <&A53_0>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> core1 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu = <&A53_1>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> core2 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu = <&A53_2>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> core3 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu = <&A53_3>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>But in arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts, <o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText style='text-indent:40.0pt'><span lang=EN-US>cpus {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> #address-cells = <2>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> #size-cells = <0>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu@0 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> device_type = "cpu";<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> compatible = "arm,cortex-a53";<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> reg = <0 0>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> next-level-cache = <&L2_0>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> cpu@1 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> device_type = "cpu";<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> compatible = "arm,cortex-a53";<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> reg = <0 1>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> next-level-cache = <&L2_0>;<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US> L2_0: l2-cache0 {<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> compatible = "cache";<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US> };<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>So, uni-processor system should not define a cpu-map node and the above vexpress-v2f-1xv7-ca53x2 fpga tile has this multiple cpus directly inside the cpus node(without wrapping with cpu-map node). So even though it is not uni-processor system, it doesn't have cpu-map node, Just cpu nodes. <o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>What does it mean? Does it mean this system doesn't support SMP? Or, I can use style without violation?<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Any comment/explanation will be very much appreciated.<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US>Thank you!<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-US><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-US>Chan Kim<o:p></o:p></span></p></div></body></html>