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<body class='hmmessage'><div dir='ltr'><p class="MsoNormal"><span lang="EN-US">Dear Experts:<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">I have some questions about the linux
timers:<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoListParagraph" style="margin-left:18.0pt;text-indent:-18.0pt;
mso-list:l0 level1 lfo1"><!--[if !supportLists]--><span lang="EN-US">1.<span style="font-stretch: normal; font-size: 7pt; font-family: 'Times New Roman';">
</span></span><!--[endif]--><span lang="EN-US">If one linux platform does not
enable CONFIG_HIGH_RES_TIMERS, it means the platform does not support high
resulution timer, what is the side effect? Is there any exact examples that can
let me know the necessary of hrtimer? For example, if hrtimer is not enabled in
code, the video 1080P will not work? I need these kind of examples to judge
whether to enable hrtimer.<o:p></o:p></span></p>
<p class="MsoListParagraph" style="margin-left:18.0pt;text-indent:-18.0pt;
mso-list:l0 level1 lfo1"><!--[if !supportLists]--><span lang="EN-US">2.<span style="font-stretch: normal; font-size: 7pt; font-family: 'Times New Roman';">
</span></span><!--[endif]--><span lang="EN-US">Suppose in one linux platform,
the timer HW is far from CPU core, if CPU wants to access timer register, it
needs to go through several bus(AXI, AHB, APB), finally the access arrives at timer
register, in this example, if I enable CONFIG_TICK_ONESHOT, and if the HZ ==
512, it means CPU core needs to call function set_next_event 512 times per
second, and the access latency caused by HW design will be large, how to
mitigate this?<o:p></o:p></span></p>
<p class="MsoListParagraph" style="margin-left:18.0pt;text-indent:-18.0pt;
mso-list:l0 level1 lfo1"><!--[if !supportLists]--><span lang="EN-US">3.<span style="font-stretch: normal; font-size: 7pt; font-family: 'Times New Roman';">
</span></span><!--[endif]--><span lang="EN-US">Suppose in one linux platform,
the system counter HW is far from CPU core, if CPU wants to access system
counter, it needs to go though several bus(AXI, AHB, APB), fianally the access arrives at
counter register, as far as I know, kernel will call update_wall_time based on
HZ, suppose HZ == 512, it means the update_wall_time will be called 512 times
per second. And inside function update_wall_time, it will read system counter
register. So the access latency caused by system counter HW design will be large,
how to mitigate this?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"> </span></p>
<p class="MsoNormal"><span lang="EN-US">Thanks in advance.<o:p></o:p></span></p> </div></body>
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