<br><br><div class="gmail_quote">On Wed, Aug 14, 2013 at 3:51 PM, nidhi mittal hada <span dir="ltr"><<a href="mailto:nidhimittal19@gmail.com" target="_blank">nidhimittal19@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5"><br><br><div class="gmail_quote">On Tue, Aug 13, 2013 at 6:02 PM, amit mehta <span dir="ltr"><<a href="mailto:gmate.amit@gmail.com" target="_blank">gmate.amit@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>On Tue, Aug 13, 2013 at 5:47 PM, nidhi mittal hada<br>
<<a href="mailto:nidhimittal19@gmail.com" target="_blank">nidhimittal19@gmail.com</a>> wrote:<br>
> thats the information of coredump file:-<br>
> KERNEL: vmlinux<br>
> DUMPFILE: vmcore.1 [PARTIAL DUMP]<br>
> CPUS: 8<br>
> DATE: Mon Jun 11 09:10:59 2012<br>
> UPTIME: 13 days, 22:39:30<br>
> LOAD AVERAGE: 83.88, 62.23, 30.30<br>
> TASKS: 393<br>
> NODENAME: <a href="http://million.ind.hp.com" target="_blank">million.ind.hp.com</a><br>
> RELEASE: 2.6.32-220.el6.hpsp16k1.x86_64<br>
> VERSION: #1 SMP Mon Nov 19 17:07:07 UTC 2012<br>
> MACHINE: x86_64 (2132 Mhz)<br>
> MEMORY: 96 GB<br>
> PANIC: "Kernel panic - not syncing: Watchdog detected hard LOCKUP on cpu 4"<br>
> PID: 26715<br>
> COMMAND: "mount.*******"<br>
> TASK: ffff8817dd4de0c0 [THREAD_INFO: ffff8802c3f80000]<br>
> CPU: 4<br>
> STATE: TASK_UNINTERRUPTIBLE (PANIC)<br>
><br>
<br>
</div>Seems, interrupts are not being re-enabled after a considerable amount of time.<br>
BTW, I'd suggest you to refrain from posting internal organizational<br>
details such<br>
as the NODENAME above, in the public mailing lists.<br>
<span><font color="#888888"><br>
!!amit<br>
</font></span></blockquote></div><br><br clear="all"></div></div>Hi Amit/Tobias,<br><br>I have understood that <br><br><u><b>for x86_64 architecture and linux as operating system , GCC as compiler , the calling convention to be followed is AMD64 ABI.</b></u><br>
right?<br><br><u><b>My doubt is :-</b></u><br>1) Is the above statement true only for stack frames function call etc ?<br>OR <br>Is the above statement true for other things related to architecture,<br>like for knowing data type sizes, endianness, alignment ..<br>
<br>as <a href="http://www.uclibc.org/docs/psABI-x86_64.pdf" target="_blank">http://www.uclibc.org/docs/psABI-x86_64.pdf</a>, mentions , data type size alignment etc everything ...<br>are these things same for AMD and x86 architecture both ???<br>
<br>2)Depending on data type, this above doc defines classes in which a specific data type lie ..<br>classes like INTEGER, MEMORY , SSE, SSEUP etc ..<br>are same things applicable in my infrastructure too <br>OR<br>they are specific to AMD architecture... if so then whats followed on x86_64 ..<br>
<br>3) is everything in this doc applicable to x86_64 or just a portion of it can be followed<br>for x86_64 ?<br><br><br><br>Thanks<span class="HOEnZb"><font color="#888888"><br>Nidhi <br><table><tbody><tr><td><br></td><td>
<br></td><td><br></td><td>
<br></td><td><br></td><td><br></td></tr><tr><td><br></td><td><br></td></tr></tbody></table><br></font></span><br></blockquote></div>And next question is ..<br><br>1)if i want to get value of a local variable, of a function, from stack trace thats bt-f output, obtained using crash ..<br>
No where AMD64 ABI mentions how local variables are stored ..<br>is it in some specific sequence of registers ? is it in stack ?<br><br>Thanks<br>Nidhi<br><br><br><br>