<div dir="ltr"><span style="font-family:arial,sans-serif;font-size:13px">>Try below points:</span><br style="font-family:arial,sans-serif;font-size:13px"><span style="font-family:arial,sans-serif;font-size:13px">>1. I am not sure about snapdragon(is it Qualcomm?) but try</span><br style="font-family:arial,sans-serif;font-size:13px">
<span style="font-family:arial,sans-serif;font-size:13px">>CONFIG_CPU_DCACHE_DISABLE.</span><br><div style><span style="font-family:arial,sans-serif;font-size:13px">I did that already, device is not booting. In our architecture cache is tightly coupled with CPU.</span></div>
<div style><span style="font-family:arial,sans-serif;font-size:13px"><br></span></div><div style><span style="font-family:arial,sans-serif;font-size:13px">>2. You are better off programming some DMA master to do large (and</span><br style="font-family:arial,sans-serif;font-size:13px">
<span style="font-family:arial,sans-serif;font-size:13px">>uncached) reads/writes to RAM and timing that.</span><br style="font-family:arial,sans-serif;font-size:13px"></div><div style><span style="font-family:arial,sans-serif;font-size:13px">DMA is not a standard way, i suppose, as it depends on what I/O peripheral we are doing the DMA. </span></div>
<div style><br></div><div style><span style="font-family:arial,sans-serif;font-size:13px">>You should always add arm mailing list and please mention the chip set details.</span><br style="font-family:arial,sans-serif;font-size:13px">
<span style="font-family:arial,sans-serif;font-size:13px">>cat /proc/cpuinfo is a great way</span><br></div><div style><div><font face="arial, sans-serif">Processor : ARMv7 Processor rev 2 (v7l)</font></div><div>
<font face="arial, sans-serif">BogoMIPS : 163.38</font></div><div><font face="arial, sans-serif">Features : swp half thumb fastmult vfp edsp neon vfpv3 tls</font></div><div><font face="arial, sans-serif">CPU implementer : 0x51</font></div>
<div><font face="arial, sans-serif">CPU architecture: 7</font></div><div><font face="arial, sans-serif">CPU variant : 0x1</font></div><div><font face="arial, sans-serif">CPU part : 0x00f</font></div><div><font face="arial, sans-serif">CPU revision : 2</font></div>
<div><br></div><div style><font face="arial, sans-serif">Thanks</font></div><div style><font face="arial, sans-serif">Sandeep</font></div></div><div style><br></div><div style><span style="font-family:arial,sans-serif;font-size:13px"><br>
</span></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Wed, Feb 27, 2013 at 5:37 PM, anish singh <span dir="ltr"><<a href="mailto:anish198519851985@gmail.com" target="_blank">anish198519851985@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar<br>
<<a href="mailto:coolsandyforyou@gmail.com">coolsandyforyou@gmail.com</a>> wrote:<br>
</div><div class="im">> Hi All<br>
> In performance benchmark tools, When we profile read/write timings mostly,<br>
> those read/writes are done to cache only.<br>
><br>
> I want to measure my DDR(RAM chip) performance.<br>
> So i want to make sure, every read/write should happen to DDR RAM chip only.<br>
</div>Try below points:<br>
1. I am not sure about snapdragon(is it Qualcomm?) but try<br>
CONFIG_CPU_DCACHE_DISABLE.<br>
2. You are better off programming some DMA master to do large (and<br>
uncached) reads/writes to RAM and timing that.<br>
<br>
However simple uncached LDR/STR from the CPU may not be a great<br>
measure of RAM controller perf.<br>
<br>
You should always add arm mailing list and please mention the chip set details.<br>
cat /proc/cpuinfo is a great way<br>
<div class="im HOEnZb">><br>
> How can i achieve this...Any ideas/suggestions...?<br>
><br>
> --<br>
> With regards,<br>
> Sandeep Kumar Anantapalli,<br>
><br>
</div><div class="HOEnZb"><div class="h5">> _______________________________________________<br>
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> <a href="mailto:Kernelnewbies@kernelnewbies.org">Kernelnewbies@kernelnewbies.org</a><br>
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><br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br>With regards,<br>Sandeep Kumar Anantapalli,<br>
</div>