<div dir="ltr">The mechanism to disable the L1/L2 memory caches of the CPU will depend on the processor architecture itself. This can be possibly be done at kernel boot-time or more preferably, in your case, through a kernel module.<div>
<br></div><div style>For Intel x86, the kernel module would look something like following: (The key is setting bit 30 of the control register cr0)</div><div style><br></div><div style><pre style="margin-top:0px;margin-bottom:10px;padding:5px;border:0px;font-size:14px;vertical-align:baseline;background-color:rgb(238,238,238);font-family:Consolas,Menlo,Monaco,'Lucida Console','Liberation Mono','DejaVu Sans Mono','Bitstream Vera Sans Mono','Courier New',monospace,serif;overflow:auto;width:auto;max-height:600px;color:rgb(0,0,0);line-height:18px">
<code style="margin:0px;padding:0px;border:0px;vertical-align:baseline;font-family:Consolas,Menlo,Monaco,'Lucida Console','Liberation Mono','DejaVu Sans Mono','Bitstream Vera Sans Mono','Courier New',monospace,serif">mov eax,cr0
or eax, 40000000H ;set bit 30 without clearing the others
mov cr0,eax</code></pre></div><div class="gmail_extra">Reference: </div><div class="gmail_extra"><a href="http://stackoverflow.com/questions/1108485/disable-l2-l1-caches">http://stackoverflow.com/questions/1108485/disable-l2-l1-caches</a></div>
<div class="gmail_extra"><a href="http://dirac.org/linux/writing/lkmpg/2.6/lkmpg-2.6.0.html">http://dirac.org/linux/writing/lkmpg/2.6/lkmpg-2.6.0.html</a></div><div class="gmail_extra"><br></div><div class="gmail_extra">~ Gaurav<br>
<br><div class="gmail_quote">On Tue, Feb 26, 2013 at 12:31 PM, sandeep kumar <span dir="ltr"><<a href="mailto:coolsandyforyou@gmail.com" target="_blank">coolsandyforyou@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div dir="ltr">Hi All<div>In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only.</div><div><br></div><div>I want to measure my DDR(RAM chip) performance.</div>
<div>
So i want to make sure, every read/write should happen to DDR RAM chip only.</div><div><br></div><div>How can i achieve this...Any ideas/suggestions...?<span class=""><font color="#888888"><br clear="all"><div><br></div>
-- <br>With regards,<br>Sandeep Kumar Anantapalli,<br>
</font></span></div></div>
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<br></blockquote></div><br><br clear="all"><div><br></div>-- <br><div dir="ltr"><font face="arial, helvetica, sans-serif">Gaurav Jain</font><div><font face="arial, helvetica, sans-serif">Associate Software Engineer</font></div>
<div><font face="arial, helvetica, sans-serif">VxVM Escalations Team, SAMG<br></font></div><div><font face="arial, helvetica, sans-serif">Symantec Software India Pvt. Ltd.</font></div><div><font face="arial, helvetica, sans-serif"><br>
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