Dear Arus,<br><br>Thanks for your reply, well I checked this commit you mentioned as following:<br>But I still could not get a clue about where the cache policy is set outside mmu.c.<br>So do you know if I put the "cachepolicy=writethrough" in cmd line, where will that be parsed?<br>
Thanks a lot! <br><br>diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c<br>index 02243ee..ea67be0 100644<br>Author: Russell King <<a href="mailto:rmk%2Bkernel@arm.linux.org.uk">rmk+kernel@arm.linux.org.uk</a>><br>Date: Sun Nov 1 17:44:24 2009 +0000<br>
<br> ARM: ensure initial page tables are setup for SMP systems<br> <br> Mapping the same memory using two different attributes (memory<br> type, shareability, cacheability) is unpredictable. During boot,<br> we encounter a situation when we're updating the kernel's page<br>
tables which can lead to dirty cache lines existing in the cache<br> which are subsequently missed. This causes stack corruption,<br> and therefore a crash.<br> <br> Therefore, ensure that the shared and cacheability settings<br>
matches the configuration that will be used later; this together<br> with the restriction in early_cachepolicy() ensures that we won't<br> create a mismatch during boot.<br> <br> Acked-by: Catalin Marinas <<a href="mailto:catalin.marinas@arm.com">catalin.marinas@arm.com</a>><br>
Signed-off-by: Russell King <<a href="mailto:rmk%2Bkernel@arm.linux.org.uk">rmk+kernel@arm.linux.org.uk</a>><br><br>diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c<br>index 02243ee..ea67be0 100644<br>--- a/arch/arm/mm/mmu.c<br>
+++ b/arch/arm/mm/mmu.c<br>@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)<br> }<br> if (i == ARRAY_SIZE(cache_policies))<br> printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");<br>
+ /*<br>+ * This restriction is partly to do with the way we boot; it is<br>+ * unpredictable to have memory mapped using two different sets of<br>+ * memory attributes (shared, type, and cache attribs). We can not<br>
+ * change these attributes once the initial assembly has setup the<br>+ * page tables.<br>+ */<br> if (cpu_architecture() >= CPU_ARCH_ARMv6) {<br> printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");<br>
cachepolicy = CPOLICY_WRITEBACK;<br>diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S<br>index 194737d..70f75d2 100644<br>--- a/arch/arm/mm/proc-v6.S<br>+++ b/arch/arm/mm/proc-v6.S<br>@@ -32,8 +32,10 @@<br>
<br> #ifndef CONFIG_SMP<br> #define TTB_FLAGS TTB_RGN_WBWA<br>+#define PMD_FLAGS PMD_SECT_WB<br> #else<br> #define TTB_FLAGS TTB_RGN_WBWA|TTB_S<br>+#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S<br> #endif<br>
<br> ENTRY(cpu_v6_proc_init)<br>@@ -222,10 +224,9 @@ __v6_proc_info:<br>--- a/arch/arm/mm/proc-v6.S<br>+++ b/arch/arm/mm/proc-v6.S<br>@@ -32,8 +32,10 @@<br> <br> #ifndef CONFIG_SMP<br> #define TTB_FLAGS TTB_RGN_WBWA<br>
@@ -32,8 +32,10 @@<br> <br> #ifndef CONFIG_SMP<br> #define TTB_FLAGS TTB_RGN_WBWA<br>+#define PMD_FLAGS PMD_SECT_WB<br> #else<br> #define TTB_FLAGS TTB_RGN_WBWA|TTB_S<br>+#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S<br>
#endif<br> <br> ENTRY(cpu_v6_proc_init)<br>@@ -222,10 +224,9 @@ __v6_proc_info:<br> .long 0x0007b000<br> .long 0x0007f000<br> .long PMD_TYPE_SECT | \<br>- PMD_SECT_BUFFERABLE | \<br>
- PMD_SECT_CACHEABLE | \<br> PMD_SECT_AP_WRITE | \<br>- PMD_SECT_AP_READ<br>+ PMD_SECT_AP_READ | \<br>+ PMD_FLAGS<br> .long PMD_TYPE_SECT | \<br>
PMD_SECT_XN | \<br> PMD_SECT_AP_WRITE | \<br>diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S<br>index 23ebcf6..eeeed01 100644<br>--- a/arch/arm/mm/proc-v7.S<br>+++ b/arch/arm/mm/proc-v7.S<br>
@@ -33,9 +33,11 @@<br> #ifndef CONFIG_SMP<br> /* PTWs cacheable, inner WB not shareable, outer WB not shareable */<br> #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB<br>+#define PMD_FLAGS PMD_SECT_WB<br> #else<br> /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */<br>
#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA<br>+#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S<br> #endif<br> <br> ENTRY(cpu_v7_proc_init)<br>@@ -326,10 +328,9 @@ __v7_proc_info:<br> .long 0x000f0000 @ Required ID value<br>
.long 0x000f0000 @ Mask for ID<br> .long PMD_TYPE_SECT | \<br>- PMD_SECT_BUFFERABLE | \<br>- PMD_SECT_CACHEABLE | \<br> PMD_SECT_AP_WRITE | \<br>- PMD_SECT_AP_READ<br>
+ PMD_SECT_AP_READ | \<br>+ PMD_FLAGS<br> .long PMD_TYPE_SECT | \<br> PMD_SECT_XN | \<br> PMD_SECT_AP_WRITE | \<br><br>Cheers,<br>Jacky<br><div class="gmail_quote">
On Tue, May 29, 2012 at 6:07 PM, Arun KS <span dir="ltr"><<a href="mailto:getarunks@gmail.com" target="_blank">getarunks@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0pt 0pt 0pt 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
Hello Jacky,<br>
<div class="im"><br>
On Tue, May 29, 2012 at 10:09 AM, <a href="mailto:h.t.jacky@gmail.com">h.t.jacky@gmail.com</a><br>
<<a href="mailto:h.t.jacky@gmail.com">h.t.jacky@gmail.com</a>> wrote:<br>
> Hi Cunsuo,<br>
><br>
> Thanks for you prompt reply.<br>
> But I'm just wondering why the other policies(such as writethrough) are<br>
> abandoned, does anyone know the architecture difference?<br>
<br>
</div>They are not abandoned from architecture.<br>
<br>
If you do a git log -p on arch/arm/mm/mmu.c, this is what we get.<br>
<br>
commit 4b46d6416548fb6a0940dfd9911fd895eb6247b3<br>
Author: Russell King <<a href="mailto:rmk%2Bkernel@arm.linux.org.uk">rmk+kernel@arm.linux.org.uk</a>><br>
Date: Sun Nov 1 17:44:24 2009 +0000<br>
<br>
ARM: ensure initial page tables are setup for SMP systems<br>
<br>
Mapping the same memory using two different attributes (memory<br>
type, shareability, cacheability) is unpredictable. During boot,<br>
we encounter a situation when we're updating the kernel's page<br>
tables which can lead to dirty cache lines existing in the cache<br>
which are subsequently missed. This causes stack corruption,<br>
and therefore a crash.<br>
<br>
Therefore, ensure that the shared and cacheability settings<br>
matches the configuration that will be used later; this together<br>
with the restriction in early_cachepolicy() ensures that we won't<br>
create a mismatch during boot.<br>
<br>
Acked-by: Catalin Marinas <<a href="mailto:catalin.marinas@arm.com">catalin.marinas@arm.com</a>><br>
Signed-off-by: Russell King <<a href="mailto:rmk%2Bkernel@arm.linux.org.uk">rmk+kernel@arm.linux.org.uk</a>><br>
<br>
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c<br>
index 02243ee..ea67be0 100644<br>
--- a/arch/arm/mm/mmu.c<br>
+++ b/arch/arm/mm/mmu.c<br>
@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)<br>
}<br>
if (i == ARRAY_SIZE(cache_policies))<br>
printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");<br>
+ /*<br>
+ * This restriction is partly to do with the way we boot; it is<br>
+ * unpredictable to have memory mapped using two different sets of<br>
+ * memory attributes (shared, type, and cache attribs). We can not<br>
+ * change these attributes once the initial assembly has setup the<br>
+ * page tables.<br>
+ */<br>
<div class="im"> if (cpu_architecture() >= CPU_ARCH_ARMv6) {<br>
printk(KERN_WARNING "Only cachepolicy=writeback<br>
supported on ARMv6 and later\n");<br>
cachepolicy = CPOLICY_WRITEBACK;<br>
<br>
</div>Thanks,<br>
Arun<br>
<div class="HOEnZb"><div class="h5">><br>
> Cheers,<br>
> Jacky<br>
> Sent from my HTC<br>
><br>
><br>
> ----- Reply message -----<br>
> From: "Cunsuo Guo" <<a href="mailto:cunsuo.guo@gmail.com">cunsuo.guo@gmail.com</a>><br>
> To: "Jacky lin" <<a href="mailto:h.t.jacky@gmail.com">h.t.jacky@gmail.com</a>><br>
> Cc: <<a href="mailto:kernelnewbies@kernelnewbies.org">kernelnewbies@kernelnewbies.org</a>><br>
> Subject: cache policy of arm mmu<br>
> Date: Tue, May 29, 2012 09:10<br>
><br>
><br>
> Hi Jacky，<br>
> I think the information of printk has already tell us the reason.<br>
><br>
> 2012/5/29 Jacky lin <<a href="mailto:h.t.jacky@gmail.com">h.t.jacky@gmail.com</a>>:<br>
>> Hi all,<br>
>><br>
>> I found that the cache policy in after ARMv6 is always set as writeback<br>
>> mode<br>
>> in mmu.c.<br>
>><br>
>> static int __init early_cachepolicy(char *p)<br>
>> {<br>
>> ...<br>
>> if (cpu_architecture() >= CPU_ARCH_ARMv6) {<br>
>> printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6<br>
>> and later\n");<br>
>> cachepolicy = CPOLICY_WRITEBACK;<br>
>> }<br>
>> ...<br>
>> }<br>
>><br>
>> Does anyone know why and provide some documents or links for that?<br>
>><br>
>> Thanks so much!<br>
>><br>
>> Cheers,<br>
>> Jacky<br>
>><br>
>> _______________________________________________<br>
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>><br>
><br>
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</div></div></blockquote></div><br>