Do you have a read barrier in the IRQ?<div><br></div><div>See "<span style="white-space:pre-wrap">SMP BARRIER PAIRING" in:</span></div><div><span style="white-space:pre-wrap"><br></span></div><div><a href="http://www.kernel.org/doc/Documentation/memory-barriers.txt">http://www.kernel.org/doc/Documentation/memory-barriers.txt</a></div>
<div><br></div><div>-- Wink</div><div><br><div class="gmail_quote">On Wed, Apr 11, 2012 at 4:59 AM, Christopher Harvey <span dir="ltr"><<a href="mailto:chris@basementcode.com">chris@basementcode.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">On 10.04.2012 19:58, Wink Saville wrote:<br>
> Sounds to me like there needs to be a flush of the processor cache<br>
> by using memory barriers.<br>
<br>
</div>I used a wmb(); right after I set the value I wanted.<br>
<div class="im"><br>
> I'm guessing that the IRQ is taken on a different thread and possibly<br>
> a different processor and the value needs to be flushed. You might<br>
> try having devid be an atomic_t and then use atomic_set<br>
> and atomic_read so that the "proper" memory barriers are used.<br>
<br>
</div>should I use atomic ops instead of a wmb?<br>
The interrupt can't happen until the value is assigned completely in<br>
one thread. I'm sure.<br>
<div class="HOEnZb"><div class="h5"><br>
<br>
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