Hi,<div><br><div>>You didn't mention exactly when you're enabling the data cache. If<br>>it's prior to executing the kernel, then your code needs to make sure<br>>that the MMU (and hence the data cache) has been disabled prior to<br>
>running the kernel itself.<br><br>>The kernel will then turn the MMU, data and instruction caches on as<br>>part of its own initialization. </div><div><br></div><div>We donot have any bootloader.,so all the necessary initialisations are done using Trace32 cmm script.</div>
<div>In this Trace32 script I am making sure that i am turning off MMU before i entering kernel as the dcahe is enable prior to kernel.</div><div><br></div><div>I could see the following console message( in red ) through early printk -- </div>
<div><br></div><div><p class="MsoNormal"><span style="color:red"><5>Linux version 3.1.6-00002-g527439a-dirty
(karthik@swaminathan-linuxpc) (gcc version 4.5.3 (Ubuntu/Linaro
4.5.3-7ubuntu1~ppa4) ) #82 Wed Mar 28 10:30:35 EDT 2012</span></p>
<p class="MsoNormal"><span style="color:red">CPU: ARM926EJ-S [+08080C888CPU: TTTTta cache,,,,VVVVnstruction cache</span></p>
<p class="MsoNormal"><span style="color:red"> </span></p>
<p class="MsoNormal"><span style="color:red">5TEJ), cr=+004444Machine:
FFFF6666oooo</span></p>
<p class="MsoNormal"><span style="color:red"> </span></p>
<p class="MsoNormal"><span style="color:red">nstruction cache</span></p>
<p class="MsoNormal"><span style="color:red"> </span></p>
<p class="MsoNormal"><span style="color:red">5TEJ), cr=+004444<5>Ignoring RAM
aaaa000000000000<3>INITRD: 0xxxx22220000<5></span></p>
<p class="MsoNormal"><span style="color:red">lowmem_limit :0x++++Memory policy: ECCCCiiiiled, Data cache
wwwweeeekkkky region - disabling initrd</span></p>
<p class="MsoNormal"><span style="color:red"><b><0>Kernel panic - not syncinggggRRRR::::iiii aaaacccc</b></span></p>
<p class="MsoNormal"><span style="color:red"> </span></p>
<p class="MsoNormal"><span style="color:red">isabling initrd</span></p>
<p class="MsoNormal"><span style="color:red">[[[[888800002222
wwww____kkkkccccfrom
222200006666]]]]nnnnppppaaaaaaaa</span></p>
<p class="MsoNormal"><span style="color:red"> </span></p>
<p class="MsoNormal"><span style="color:red">[[[[000066662222
wwwwppppaaaaccccfrom
222200002222]]]]nnnniiiiaaaaaaaa</span></p>
<p class="MsoNormal"><span style="color:red"> </span></p>
<p class="MsoNormal"><span style="color:red">[[[888822222222
wwwwiiiiaaaaccccfrom
22226666EEEE]]]]nnnnbbbbkkkkllllbbbb++////0000)</span></p>
<p class="MsoNormal"><span style="color:red">[[[[6666EEEE0000
wwwwbbbbkkkkllllbbbb++++////0000rom [[[[6666EEEE0000 wwwwbbbbkkkkllllbbbb++++////0000++++/)</span></p>
<p class="MsoNormal"><span style="color:red">[[[[6666EEEE0000
wwwwbbbbkkkkllllbbbb++++////0000++++////++++////rom [[[[6666AAAA04>]
(unwllllllll++++////)</span></p>
<p class="MsoNormal"><span style="color:red">[[[[6666AAAA0000
wwwwllllllll++++////rom [[[[88882222AAAA wwwwiiiiiiii++++AAAA04>]
(unwllllllll++++////)</span></p>
<p class="MsoNormal"><span style="color:red">[[[[88882222AAAA
wwwwiiiiiiii++++rom [[[[888822220000
wwwwuuuurrrr++++++++AAAA04>] (unwllllllll++++////)</span></p>
<p class="MsoNormal"><span style="color:red">[[[[6666CCCC0000
ttttaaaa++++) from
[<<<<666644444444((((wwwwuuuurrrr++++++++AAAA04>]
(unwllllllll++++////)</span></p>
<p class="MsoNormal"><span style="color:red">[[[[666644440000
from 222200000000]]]]</span></p>
<p class="MsoNormal"><span style="color:red"> </span></p>
<p class="MsoNormal"><span style="color:red">44444444((((wwwwuuuurrrr++++++++AAAA04>]
(unwllllllll++++////).</span></p><p class="MsoNormal"><span style="color:red"><br></span></p><p class="MsoNormal"></p><p class="MsoNormal">We
could see control going to panic(shown in bold.).</p>
<p class="MsoNormal"> </p>
<p class="MsoNormal">Please
let me know how dcahe enabling is resulting in panic., with dcache
disabled(CPU_DCACHE_DISABLE = y) everything seems to be OK.</p><p></p></div><div><br></div><div><br><br><div class="gmail_quote">On Tue, Mar 27, 2012 at 9:32 PM, Dave Hylands <span dir="ltr"><<a href="mailto:dhylands@gmail.com">dhylands@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Karthiik,<br>
<div class="im"><br>
On Tue, Mar 27, 2012 at 5:12 AM, KARTHIK SEKURU<br>
<<a href="mailto:karthik.sekuru@gmail.com">karthik.sekuru@gmail.com</a>> wrote:<br>
> Hi,<br>
><br>
> I'm doing kernel porting to arm926 based FPGA board, very minimal setup.<br>
</div>...snip...<br>
<div class="im">> If I enable data cache and debug with JTAG, Kernel ends up in<br>
> ENTRY(__delay).<br>
<br>
</div>So you mentioned enabling the data cache. So on the ARM, enabling the<br>
data cache means that the MMU has to be enabled.<br>
<br>
There is a "rule" that the MMU MUST be off when the kernel starts, or<br>
things won't work properly.<br>
<a href="http://lxr.linux.no/linux+v3.3/Documentation/arm/Booting#L159" target="_blank">http://lxr.linux.no/linux+v3.3/Documentation/arm/Booting#L159</a><br>
<br>
You didn't mention exactly when you're enabling the data cache. If<br>
it's prior to executing the kernel, then your code needs to make sure<br>
that the MMU (and hence the data cache) has been disabled prior to<br>
running the kernel itself.<br>
<br>
The kernel will then turn the MMU, data and instruction caches on as<br>
part of its own initialization.<br>
<span class="HOEnZb"><font color="#888888"><br>
--<br>
Dave Hylands<br>
Shuswap, BC, Canada<br>
<a href="http://www.davehylands.com" target="_blank">http://www.davehylands.com</a><br>
</font></span></blockquote></div><br></div></div>