<br><br><div class="gmail_quote">On Tue, May 24, 2011 at 6:15 PM, Ashok Babu <span dir="ltr"><<a href="mailto:ashok3d@gmail.com" target="_blank">ashok3d@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi All,<div><br></div><div>I am no success in booting up the ARM1176 processor with the linux-2.6.32 kernel.</div><div><br></div><div>While googling about the ARM Harvard architecture, I came to know that we have to flush/invalidate the D-Cache and I-Cache </div>
<div>when using the self modifying codes.</div><div><br></div><div>So here my questions/doubts :</div><div>1) Is'nt it the kernel itself is self modifying code with lots of function pointers ?</div><div> If yes, how is synchronization b/w d-cache and i-cache handled in the kernel ?</div>
<div>2) Can this be the reason for the kernel not booting for me ?</div><div> Because If i disable the I-Cache in the config, then the kernel boots up without any issues.</div><div><br></div><div>Any pointers on this will be of great help.</div>
<div><br></div></blockquote><div>Here:</div><div><br></div><div><a href="http://blogs.arm.com/software-enablement/141-caches-and-self-modifying-code/" target="_blank">http://blogs.arm.com/software-enablement/141-caches-and-self-modifying-code/</a></div>
<div><br></div><div>read the part on "The Solution" - it describe function pointer on a register, and what u are supposed to do with cache transfer. (java is full of JIT compilation)</div><div><a href="http://blogs.arm.com/software-enablement/141-caches-and-self-modifying-code/" target="_blank"></a> </div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div></div><div>Thanks & Best Regards</div><div>Ashok</div><font color="#888888"><div> <br><div><br></div><div><br></div></div>
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<br></blockquote></div><br><br clear="all"><br>-- <br>Regards,<br>Peter Teoh<br>