Hello.<br><br>Please do not hesitate to let me know if this must be posted elsewhere.<br><br>I have been trying to understand the code that sets up the MMU. I do have a fair understanding of the way MMU is meant to be setup, but something in the kernel code is tripping me.<br>
<br>The code that kickstarts setting up of MMU is __create_page_tables in /arch/arm/kernel/head.S.<br><br>This code is position independent.<br><br>It basically <br>- Reserves 16KB of memory in RAM just before the start of the uncompressed kernel.<br>
- Clears the 16KB meant to serve as L1 lookup table containing 4096 entries<br>- Creates a section entry in L1 table for the kernel code to be mapped into physical memory<br><br>It is this creation of section entry code that is puzzling me.<br>
<br>The index used to program this entry is based on physical address of the kernel base. <br><br>The way it ought to work is this. When the CPU issues a virtual address, the top bits are used as an index into this L1 table and then through a couple of table walk throughs, the physical address is arrived at. So the index used to program the L1 table ought to have been <br>
<br>Now look at this code.<br><br>__create_page_tables:<br> pgtbl r4 @ page table address<br><br> /*<br> * Clear the 16K level 1 swapper page table<br> */<br> mov r0, r4 @r0 = 0x80004000<br>
mov r3, #0<br> add r6, r0, #0x4000 @r6 = 0x80008000 <br>1: str r3, [r0], #4<br> str r3, [r0], #4<br> str r3, [r0], #4<br> str r3, [r0], #4<br> teq r0, r6<br> bne 1b<br>
<br><br> /* r10 contains proc_info pointer */<br> ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags<br><br> /*<br> * Create identity mapping to cater for __enable_mmu.<br> * This identity mapping will be removed by paging_init().<br>
*/<br> adr r0, __enable_mmu_loc<br> ldmia r0, {r3, r5, r6}<br><br> sub r0, r0, r3 @ virt->phys offset<br> add r5, r5, r0 @ phys __enable_mmu<br> add r6, r6, r0 @ phys __enable_mmu_end<br>
<br> mov r5, r5, lsr #20<br> mov r6, r6, lsr #20<br><br>1: orr r3, r7, r5, lsl #20 @ flags + kernel base<br> str r3, [r4, r5, lsl #2] @ identity mapping<br><br> teq r5, r6<br>
addne r5, r5, #1 @ next section<br> bne 1b<br><br> <br>The 2 lines above <br>1: orr r3, r7, r5, lsl #20 @ flags + kernel base ==> Correct<br>
str r3, [r4, r5, lsl #2] @ identity mapping ==> ??<br>
<br>create a section entry using index based on physical address. <br><br>Am I missing something here?<br><br>Regards,<br>Prakash<br>