Sir,<br><br><div>Thank you very much for the explanation.</div><div><br><div class="gmail_quote">On Wed, Feb 16, 2011 at 8:20 PM, Bruce Rowen <span dir="ltr"><<a href="mailto:browen@aoc.nrao.edu">browen@aoc.nrao.edu</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">When the interrupt line is asserted by the hardware device (could be<br>
a peripheral, whatever) the interrupt controller decides how to pass<br>
this signal onto the processor. Some controllers will prioritize the<br>
interrupt based on the interrupt line number. For example, assume line<br>
#3 has interrupted. If line #4 then interrupts and #4 has higher<br>
priority, the service routine for interrupt line #3 will itself be<br>
interrupted. If a lower priority interrupt (say #2) occurs, then #3<br>
will continue until completion at which point #2 will be serviced.<br>
Note that this hardware prioritization is highly dependent on hardware<br>
and hardware setup. It could be such that an incoming interrupt with a<br>
lower priority than a currently servicing interrupt is simply ignored.<br></blockquote><div><br></div><div>If that is the case,</div><div>1) What happens in the case of x86?</div><div>2) Can we configure hardware (say, I/O APIC) so that alway higher priority interrupt's handler runs first?</div>
<div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<br>
Mulyadi is correct in that once this hardware interrupt has been<br>
acknowledged at the controller and the (usually very short) interrupt<br>
service routine has been run, the prioritization of the rest of the<br>
interrupt handler is left to the Kernel. Typically in most systems the<br>
NMI has the highest priority and of course given its name, can never<br>
be ignored (masked).<br>
<br>
-Bruce<br>
<div><div></div><div class="h5"><br>
On Feb 16, 2011, at 1:54 AM, Mulyadi Santosa wrote:<br>
<br>
> Hi :)<br>
><br>
> On Tue, Feb 15, 2011 at 19:20, Darshan Ghumare<br>
> <<a href="mailto:darshan.ghumare@gmail.com">darshan.ghumare@gmail.com</a>> wrote:<br>
>> IMHO, When the Processor is executing interrupt handler of IRQ4 then<br>
>> Processor is the one which pushes SS, SP, EFLAGS, CS & EIP on<br>
>> stack (in<br>
>> this case this will all corresponds to interrupt handler of IRQ4) &<br>
>> loads CS<br>
>> & EIP corresponding to IRQ5.<br>
>> So, how come its depends on OS (kernel)? Please correct me if I am<br>
>> wrong.<br>
><br>
> OK, to make it clear, I was talking about bottom half prioritizing<br>
> .... the upper half is reacting whenever interrupt is coming (and it<br>
> is not currently masked/disabled) AFAIK. Bottom half is the part where<br>
> OS could do prioritizing if it indeed does so.<br>
><br>
> The only "prioritizing" (if you take it as prioritizing) in interrupt<br>
> is when it is fall into NMI (Non Maskable Interrupt). AFAIK, they<br>
> could just kick others in queue, just like real time task kick regular<br>
> process :) Uhm, maybe watchdog timer does same kind of interrupt<br>
> too...<br>
><br>
> Guys, CMIIW here...<br>
><br>
> --<br>
> regards,<br>
><br>
> Mulyadi Santosa<br>
> Freelance Linux trainer and consultant<br>
><br>
> blog: <a href="http://the-hydra.blogspot.com" target="_blank">the-hydra.blogspot.com</a><br>
> training: <a href="http://mulyaditraining.blogspot.com" target="_blank">mulyaditraining.blogspot.com</a><br>
><br>
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</blockquote></div><br><br>
</div>