<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Feb 16, 2011, at 9:49 PM, Darshan Ghumare wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Sir,<br><br><div>Thank you very much for the explanation.</div><div><br><div class="gmail_quote">On Wed, Feb 16, 2011 at 8:20 PM, Bruce Rowen <span dir="ltr"><<a href="mailto:browen@aoc.nrao.edu">browen@aoc.nrao.edu</a>></span> wrote:<br> <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">When the interrupt line is asserted by the hardware device (could be<br> a peripheral, whatever) the interrupt controller decides how to pass<br> this signal onto the processor. Some controllers will prioritize the<br> interrupt based on the interrupt line number. For example, assume line<br> #3 has interrupted. If line #4 then interrupts and #4 has higher<br> priority, the service routine for interrupt line #3 will itself be<br> interrupted. If a lower priority interrupt (say #2) occurs, then #3<br> will continue until completion at which point #2 will be serviced.<br> Note that this hardware prioritization is highly dependent on hardware<br> and hardware setup. It could be such that an incoming interrupt with a<br> lower priority than a currently servicing interrupt is simply ignored.<br></blockquote><div><br></div><div>If that is the case,</div><div>1) What happens in the case of x86?</div></div></div></blockquote><div><br></div><div>Depends on the interrupt controller. Common systems have interrupt controllers embedded into 'glue' chips such as a 'Southbridge' or 'Northbridge'.</div><div>To find the exact device and functionality you will need to consult the hardware manuals for your system.</div><br><blockquote type="cite"><div><div class="gmail_quote"><div>2) Can we configure hardware (say, I/O APIC) so that alway higher priority interrupt's handler runs first?</div> </div></div></blockquote><br></div><div>My experience with small form-factor (pc104) X86 is that much of the setup/assignments of priority is done in the BIOS. I found it to be complex to change the assignments after the kernel is running so your best chance is to use the features of your BIOS.</div><div><br></div><div>Remember that the ISR typically exists as only a handful of lines of code. Its job is to determine that its hardware was the one interrupting (for when hardware shares interrupt lines), do whatever hardware changes are required (clear interrupt flags, acknowledge DMA, etc.), and then tell the kernel to schedule the rest of the handler (tasklet/bottom half, etc.). </div><div>A truly prioritized interrupt would allow the higher level interrupt to preempt the running of a lower levels ISR and tasklet. A lower level interrupt would be held off until the higher level interrupts ISR has completed, but it then could preempt the running of the higher level interrupts tasklet. </div><div>Once all interrupts are scheduled to run as tasklets, it is the order they are queued that determines their run order (last in, first run).</div><div><br></div><div>For example, scheduling the tasklet for a higher level interrupt with tasklet_hi_schedule() will allow it to run before those scheduled with tasklet_schedule(). </div><div><br></div><div>Thus there are two places to control interrupt servicing priorities. The hardware level which allows preemption during the microseconds long hardware ISR code, and the software (tasklet) level that has priorities assigned by scheduling methods and scheduling order.</div><div><br></div><div>-Bruce</div><div><br></div><div><br></div><div><br></div><div><br></div><br></body></html>