Exchanging data between CPU and FPGA through shared DDR

[Patryk]

Hi,
I'm working on a SoC where both the CPU and an FPGA have access to the same
DDR memory. I need to exchange data between them.
One idea I have is to reserve a portion of DDR via the device tree
(reserved-memory node), so that the kernel will not use it, and then use
ioremap (or similar) to expose that region to user space so an application
can communicate with the FPGA.
Is this the right approach, or is there a more recommended mechanism in the
kernel for CPU - FPGA data exchange using shared DDR?

Best regards
Patryk
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