RISC-V and interrupts, constant rate vs. tickless vs. SIE=0

[Andras Pal]

Hi All,

I'm compiling and installing the RISC-V (RV32IMAC) port of Linux to a 
custom FPGA-based SoC. However, during the ISA level simulations, there is 
an indication that do_idle() disables the supervisor interrupts by setting 
SIE=0 in the CSR sstatus, just before entering to WFI state. It happens 
right after starting the /init process from initrd, so when the 
(presumably) first U mode precess is executed and this process is just 
waiting from interrupts from the console (that is a 8250/16550, connected 
to SEI via PLIC).

I tried both tickless and constant rate timers in Config > General setup > 
Timers subsystem, but both of them behaves the same. If the system is 
tickless, it might make sense to disable STIE in the CSR sie, but not SIE 
in sstatus... How can this issue be debugged or checked in more details, 
do you have any recommendations where to start?

The kernel version is one of the most recent longterm one (6.6.32, to be 
precise).

thanks in advance, Andras