The method to alloc DMA ring buffer

[Tom Mitchell]

On Tue, Dec 6, 2022 at 8:17 PM Tony He <huangya90 at gmail.com> wrote:
...
>
> I'm studying the NIC driver with the book <<Understanding the linux
> network internals>>. This book uses 3com 3c59x NIC(3c59x.c) as an
> example. The driver is very old and few people discuss it, but it's a
> good place to start because it's simpler than many other drivers with
> advanced offload features.
>
> In the interrupt handler boomerang_rx(), I see it pre-allocate one new
...

>     goto clear_complete;
Oh m a goto.
...
> However, I see intel e1000 driver optimizes this. Intel doesn't
> pre-allocate one at a time.
....
> I just want to know why this is faster. For all scenarios or some
> scenarios? Can someone analyse it rigorously?

The first step is to examine the hardware data pages.
Most optimizations like this are shaped by hardware

That said, buffer allocation in the kernel is slow(ish).
Any time there is sufficient ram to preallocate, do so in moderation.
...
Interrupt latency.
It helps to have the hardware address a list of commands in a queue without
hardware intervention.
Networking:
a buffer window sent to the client  allows that client to send data
without waiting on
a response and is unlikely to need to resend unless the network has loss.

The networking buffer window strategy is a giant topic.

Interrupt latency: that is another book  and it depends on the hardware.  Again
any hardware that can do useful work without interrupt servicing the better.

Simple serial IO hardware drivers can be easier to research and analyze.
Again start with the hardware data sheets for UARTS and hardware and software
flow control over serial data links.

Define: rigorously?  Is this a homework assignment?