A question about regmap bus

[Clyde Huang31]

Hi All,

We have an FPGA device and it is connect to a SOC through the SPI interface.
The communication is using a specific protocol like as bellow.

Read a register:
           <                       Bits                         >
           ++++++++++++++++++++++++++++++++++++++++++++++++++++++
           |  7   |  6  |  5  |  4  |  3  |  2  |   1   |   0   |
^  ++++++++|++++++|+++++|+++++|+++++|+++++|+++++|+++++++|++++++++
   | 0      |  0   |               Header (6:0)                   | 
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | 1      |       Header (7:2)                  |  Address (1:0)   |
B  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
y  | 2      |                  Address (7:0)                       |
t  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
e  | 3      |                Data Count (7:0)                      |
s  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | 4      |              Turn-Around-Time (7:0)                  |
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | 5...X   |          X bytes data from the SPI slave                 |
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | N-1    |             Status from the SPI slave                   |
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | N     |              CRC from the SPI slave                    |
v  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  
Write a register:
           <                       Bits                         >
           ++++++++++++++++++++++++++++++++++++++++++++++++++++++
           |  7   |  6  |  5  |  4  |  3  |  2  |   1   |   0   |
^  ++++++++|++++++|+++++|+++++|+++++|+++++|+++++|+++++++|++++++++
   | 0      |  0   |               Header (6:0)                   |
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | 1      |       Header (7:2)                 |   Address (1:0)   |
B  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
y  | 2      |                  Address (7:0)                       |
t  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
e  | 3      |                Data Count (7:0)                      |
s  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   |  4...X  |           X bytes data to the SPI slave                  |
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | N-3    |              CRC to the SPI slave                      | 
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | N-2    |                Turn-Around-Time                     |
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | N-1    |             Status from the SPI slave                   |
   ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
   | N     |              CRC from the SPI slave                    |
v  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

The protocol seems like needs a new rebmap bus to support it. Is that right?

I see a similer design in drivers/base/regmap/regmap-spi-avmm.c and know it is for Intel Avalon bus. 
A new question is, if the protocol is only for a specific SPI device. 
Should I generate a new regmap bus driver into drivers/base/regmap folder? 
or this regmap bus should implement together with the SPI device driver in the same file? 
I found an example is devm_regmap_init() function called in drivers/mfd/atmel-hlcdc.c file.

T