How to measure the RAM read/write performance

[Arun KS]

On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi <ankurengg2003 at gmail.com> wrote:
> I am not sure but what if you make the variable as a volatile?

Volatile in simple terms
==================
Consider this eg:

1  int main(void){
2  int a, x, y;
3  x=a;
4  y=a;
5  }

Line 3 with be converted to a LDR instruction.
Line 4 is where the compiler optimization comes in. It may be loaded
from the previous loaded register.

Line 3: ldr r0[r1];   r1 is having the address of a
Line 4: mov r2 r0;   because we have value of a already in r0.

But if a is volatile variable, then compiler places ldr for both
instructions(ie for x=a and y = a).
so line 4 will change as follows.

Line 3: ldr r0[r1];    r1 is having the address of a
Line 4: ldr r2[r1];     r1 is having the address of a

But if cache is enabled, ldr can fetch the data from cache if present.
So volatile cannot help us here.

Thanks,
Arun

>
> On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar <coolsandyforyou at gmail.com>
> wrote:
>>
>> Hi All
>> In performance benchmark tools, When we profile read/write timings mostly,
>> those read/writes are done to cache only.
>>
>> I want to measure my DDR(RAM chip) performance.
>> So i want to make sure, every read/write should happen to DDR RAM chip
>> only.
>>
>> How can i achieve this...Any ideas/suggestions...?
>>
>> --
>> With regards,
>> Sandeep Kumar Anantapalli,
>>
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>
>
>
> --
> Thanks
>
> Ankur Dwivedi
>
>
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