interrupt handler in arm question

[subin gangadharan]

Hi Kosta,

Thanks for answering.I really appreciate you taking the time to answer
my question.


On Sun, Dec 11, 2011 at 10:07 AM, Konstantin Zertsekel
<zertsekel at gmail.com> wrote:
>> 2) In case of FIQ mode to which routine it jumps to,basically in IRQ
>> mode it jumps to    either __irq_svc or __irq_usr as you explained
>> earlier.
>>    I have looked at the source code, but I couldn't figure out in
>> case of FIQ, where its    branching to.
>
> That's for a good reason :-)
> FIQ exception is not implemented in Linux Kernel.
> Actually, when ARM CPU takes FIQ exception, it branches to 0xffff001c
> address, which contains the below code from entry-armv.S:
> vector_fiq:
>        disable_fiq
>        subs    pc, lr, #4
>
> Now, disable_fiq not implemented for all the platforms.
> But, anyway, 'subs pc, lr, #4' returns the CPU to the point where
> FIQ exception has happened and the system continues to run as usual.

As you said, disable_fiq is empty in OMAP architecture.
.macro  disable_fiq
.endm

So from the above explanation,I can saythat LINUX is not making use of
FIQ feature of arm.Am I right?


>
>>>> I am trying to understand how the interrupt handler in arm working.By
>>>> looking at the code,what I understood,when an interrupt
>>>> happens arm disables the irq, saves the cpsr to spsr,save current pc
>>>> to lr and switches to irq mode.
>>>
>>> Yes, that's right.
>>> Important to understand that IRQ processor mode has its (mode-private)
>>> own sp, lr and spsr registers.
>>> Additionally, mode-private registers (sp, lr and spsr) are
>>> inaccessible from other modes.
>
>>>> So in case of interrupt it branches to the vector_irq and there it
>>>> saves some registers and depending on which context
>>>> its happened,it will call __irq_user or __irq_svc. But before that it
>>>> switches to the supervisory mode.
>
>>> That's right. In Linux Kernel the IRQ, Data Abort, Prefetch Abort, SWI
>>> and Undefined exceptions
>>> are handled in SVC processor mode. In Linux SVC processor mode of ARM
>>> CPU is called "Kernel mode".
>>> You have to switch to SVC processor mode from IRQ (and other processor
>>> modes) to enabled reentrant
>>> interrupts.
>>> Simplistically, it works like this: (1) IRQ exception is entered, (2)
>>> spsr_irq, r0 and lr_irq is saved
>>> on the private IRQ stack (its size is only 12 bytes), (3)
>>> 'vector_stub' macro check from what
>>> processor mode we got here - kernel mode or user mode - and calculates
>>> what to call __irq_user
>>> or__irq_svc and (4) the last thing it does 'movs pc, lr' which loads
>>> spsr_irq into cpsr and puts lr
>>> into pc (lr now contains __irq_svc or __irq_user and spsr_irq[4:0]
>>> contains SVC mode bits).
>>> Mind, that r0 points to private IRQ stack that contains original r0,
>>> lr_irq and spsr_irq.
>
>> 1) Does the LINUX handles the interrupt like this in all other
>> architectures.I mean handler will always be executed in SVC mode.
>
> Sorry, I am too unfamiliar with other architectures... to my detriment actually.
> Can anybody fill the knowledge gap here?!
>
> --- Kosta



-- 
With Regards
Subin Gangadharan

I am not afraid and I am also not afraid of being afraid.